Exploiting state encoding for invariant generation in induction-based property checking

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 424-429

  Wedler, Markus ^a   Stoffel, Dominik ^a   Kunz, Wolfgang ^a  

^a Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; COMPUTATIONAL METHODS; GRAPH THEORY; NETWORKS (CIRCUITS); PROBLEM SOLVING; SET THEORY; THEOREM PROVING;

DESIGN AUTOMATION; FINITE STATE MACHINES; INDUCTION;

ENCODING (SYMBOLS);

EID: 2442542271     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Pasosh Aziz Abdulla, Per Bjesse, and Niklas E'en. Symbolic reachability analysis based on sat solvers. In Proc. Sixth International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS-00), pages 411-425, March 2000.
2. Per Bjesse and Koen Claessen. SAT-based verification without state space traversal. In Formal Methods in Computer-Aided Design, pages 372-389, 2000.
3. J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill. Symbolic model checking for sequential circuit verification. IEEE Transactions on Computer-Aided Design, 13(4):401-424, April 1994.
4. Andreas Kühlmann and Jason Baumgartner. Transformation-based verification using generalized retiming. In Proc.Intl. Conf. Computer Aided Verification(CAV-01), pages 104-117, July 2001.
5. Wolfgang Kunz and Dhiraj Pradhan. Recursive learning: A new implication technique for efficient solutions to CAD problems: Test, verification and optimization. IEEE Transactions on Computer-Aided Design, 13:1143-1158, Sep. 1994.
6. R. P. Kurshan. Computer-Aided Verification of Coordinating Processes - The Automata-Theoretic Approach. Princeton University Press, Princeton, New Jersey, 1994.
7. K.L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, Boston, 1993.
8. M.W. Moskewicz, C.F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient sat solver. In Proc. Intl. Design Automation Conference (DAC-01), pages 530-535, June 2001.
9. Mary Sheeran, Satnam Singh, and Gunnar Stalmarck. Checking safety properties using induction and a sat solver. In Proc. Intl. Conf.Formal Methods in Computer-Aided Design(FMCAD 2000), volume 1954 of Lecture Notes in Computer Science. Springer, November 2000.
10. Dominik Stoffel and Wolfgang Kunz. Record & play: A structural fixed point iteration for sequential circuit verification. In Proc. Intl. Conference on Computer-Aided Design (ICCAD-97), pages 394-399, Nov 1997.
11. C.A.J. van Eijk. Sequential equivalence checking without state space traversal. In Proc. Conference on Design, Automation and Test in Europe (DATE-98), pages 618-623, Paris, France, March 1998.
12. Markus Wedler, Dominik Stoffel, and Wolfgang Kunz. Improving structural fsm-traversal by constraint-satisfying simulation. In Proc. IEEE Computer Society Annual Symposium on VLSI 2002 (ISVLSI 2002), pages 151-158, April 2002.