On verifying the correctness of retimed circuits

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1996, Pages 277-280

  Huang, Sh Y ^a   Cheng, K T ^a   Chen, K Ch ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; EFFICIENCY; FLIP FLOP CIRCUITS; PATTERN RECOGNITION; PERFORMANCE; TESTING;

RETIMED CIRCUITS;

TIMING CIRCUITS;

EID: 0029695303     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)