Validity of retiming sequential circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1995, Pages 316-321

  Singhal, Vigyan ^a   Pixley, Carl ^a   Rudell, Richard L ^a   Brayton, Robert K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; DIGITAL CIRCUITS; LOGIC DESIGN; LOGIC GATES; SIMULATION; SIMULATORS; SYNCHRONIZATION;

LATCHES; LOGIC SIMULATION; RETIMING; TESTABILITY;

SEQUENTIAL CIRCUITS;

EID: 0029214276     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/217474.217548     Document Type: Conference Paper

References (10)