Sequential equivalence checking without state space traversal

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 618-623

  Van Eijk, C A J ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

SEQUENTIAL EQUIVALENCE CHECKING;

EQUIVALENT CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 84893769353     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655922     Document Type: Conference Paper

References (14)

1. P. Ashar, A. Gupta, and S. Malik, "Using Complete-1- Distinguishability for FSM Equivalence Checking", Proc. ICCAD, pp. 346-353, 1996.
2. J.R. Burch, et al., "Symbolic Model Checking for Sequential Circuit Verification", IEEE Trans. on Computer-Aided Design of Integr. Circ. and Syst., vol. 13, no. 4, pp. 401-424, April 1994.
3. G. Cabodi, et al., "Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits", Proc. 34th DAC, pp. 728-733, 1997.
4. H. Cho, et al., "Algorithms for Approximate FSM Traversal", Proc. 30th DAC, pp. 25-30, 1993.
5. C.A.J. van Eijk, and J.A.G. Jess, "Detection of Equivalent State Variables in Finite State Machine Verification", Workshop notes of the 1995 IWLS, pp. 3.35-3.44, 1995.
6. C.A.J. van Eijk, and J.A.G. Jess, "Exploiting Functional Dependencies in Finite State Machine Verification", Proc. ED&TC, pp. 9-14, 1996.
7. C.A.J. van Eijk, "Formal Methods for the Verification of Digital Circuits", Ph.D. Thesis, Eindhoven University of Technology, September 1997.
8. D. Eisenbiegler, R. Kumar, and C. Blumenröhr, "A Constructive Approach towards Correctness of Synthesis-Application within Retiming", Proc. ED&TC, pp. 427-431, 1997.
9. T. Filkorn, "Symbolische Methoden für die Verifikation endlicher Zustandssysteme," Dissertation Institut für Informatik der Technischen Universität München, 1992.
10. S.-Y. Huang, K.-T. Cheng, and K.-C. Chen, "On Verifying the Correctness of Retimed Circuits", Proc. Great Lakes Symp. on VLSI, pp. 277-281, 1996.
11. S.-Y. Huang, K.-T. Cheng, and K.-C. Chen, "AQUILA: An Equivalence Verifier for Large Sequential Circuits", Proc. ASPDAC, pp. 455-460, 1997.
12. S. Quer, et al., "Incremental Re-encoding for Symbolic Traversal of Product Machines", Proc. EuroDAC, pp. 158-163, 1996.
13. L. Stok, I. Spillinger, and G. Even, "Improving Initialization through Reversed Retiming", Proc. ED&TC, pp. 150-154, 1995.
14. D. Stoffel, and W. Kunz, "Record &Play: A Structural Fixed Point Iteration for Sequential Circuit Verification", Proc. ICCAD, pp. 394-399, 1997.