Effective loop partitioning and scheduling under memory and register dual constraints

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 1202-1207

  Xue, Chun Jason ^a   Sha, Edwin H M ^b   Shao, Zili ^c   Qiu, Meikang ^a,d  

^a CITY UNIVERSITY OF HONG KONG   (Hong Kong)

^b The University of Texas at Dallas   (United States)

^c HONG KONG POLYTECHNIC UNIVERSITY   (Hong Kong)

^d U of New Orleans

Author keywords

[No Author keywords available]

Indexed keywords

DATA LOCALITY; EMBEDDED APPLICATIONS; LIMITED MEMORY; LOCAL MEMORIES; LOOP PARTITIONING; LOOP PIPELINING; LOOP TRANSFORMATIONS; MEMORY LATENCIES; PARALLEL EMBEDDED SYSTEMS; PRE-FETCHING; REGISTER PRESSURE; SCHEDULE LENGTH; SCHEDULING FRAMEWORKS;

COMPUTER PROGRAMMING LANGUAGES; INDUSTRIAL ENGINEERING; INTEGRATED CIRCUITS; SCHEDULING; TESTING;

EMBEDDED SYSTEMS;

EID: 49749106589     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484842     Document Type: Conference Paper

References (11)

1. T. Azalea. Y. Kimbra. and S. Nishizaki. Cache miss heuristics and preloading techniques for general-purpose programs. Proceedings of the 28th annual ACM/IEEE international symposium on Microarchitecture, pages 243 248. 1995.
2. L.-F. Chao, A. S. LaPaugh, and E. H.-M. Sha. Rotation scheduling: A loop pipelining algorithm. IEEE Trans. on Computer-Aided Design, 16(3):229 239. March 1997.
3. F. Chen, T. W. O'Neil, and E. H.-M. Sha. Optimizing overall loop schedules using prefetching and partitioning. IEEE Transactions on Parallel and Distributed Systems, 11(6):604 614, June 2000.
4. F. Chen and E.-M. Sha. Loop scheduling and partitions for hiding memory latencies. International Symposium on System Synthesis, 1999.
5. F. Dahlgren and M. Dubois. Sequential hardware prefetching in shared-memory multiprocessors. IEEE Transaction on Parallel and Distributed Systems, pages 733 746, July 1995.
6. A. Eichenberger and E. Davidson. Stage scheduling: a technique to reduce register requirements of a modulo schedule. Proceedings of the 28th Annual International Symposium, on Microarchitecture.
7. M. Inc. Motorola dsp 563000 family manual, revision 3.0. November 2000.
8. N. Manjikian. Combining loop fusion with prefetching on shared-memory multiprocessors. International Conference on Parallel Processing, pages 78 82. 1997.
9. K. Wang, T. Yu, and E. H.-M. Sha. Recrs: A framework for loop scheduling with limited number of registers. Proceedings of the 8th IEEE Great Lakes Symposium on VLSI, February 1998.
10. Z. Wang, D. Burger, K. S. McKinley, S. K. Reinhardt, and C. C. Weems. Guided region prefetching: A cooperative hardware/software approach. Proc. of the 30th annual international symposium, on Computer architecture, pages 388 398, May 2003.
11. Z. Wang, Q. Zhuge, and E.-M. Sha. Scheduling and partitioning for multiple loop nests. International Symposium, on System Synthesis, pages 183 188, October 2001.