Loop Scheduling and Partitions for Hiding Memory Latencies

Proceedings of the International Symposium on System Synthesis

Volumn Part F129194, Issue , 1999, Pages

  Chen, Fei ^a   Sha, Edwin Hsing Mean ^a  

^a University of Notre Dame   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SCHEDULING;

DATA PRE-FETCHING; HIDING MEMORY LATENCY; ITERATION SPACES; LOOP SCHEDULING; MEMORY LATENCIES; NEAR-OPTIMAL SOLUTIONS; OPTIMAL PARTITIONS; REGULAR PARTITIONS;

ITERATIVE METHODS;

EID: 73449135115     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. F. Chen, S. Tongsima, and E. H.-M. Sha. Loop scheduling optimization with data prefetching based on multidimensional retiming. In Proc. ISCA 11th International Conference on Parallel and Distributed Computing Systems, pages 129-134, 1998.
2. F. Dahlgren and M. Dubois. Sequential hardware prefetching in shared-memory multiprocessors. IEEE Transactions on Parallel and Distributed Systems, Vol. 6, No. 7, pages 733-746, Jul. 1995.
3. N. L. Passos and Edwin H.-M. Sha. Scheduling of uniform multi-dimensional systems under resource constraints. To appear in the IEEE Transactions on VLSI systems.
4. N. L. Passos and Edwin H.-M. Sha. Achieving full parallelism using multi-dimensional retiming. IEEE Transactions on Parallel and Distributed Systems, Vol. 7, No. 11, pages 1150-1163, Nov. 1996.
5. J. Skeppstedt and M. Dubois. Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps. In the Proceedings of the International Conference on Parallel Processing, pages 298-305, 1997.
6. M. K. Tcheun, H. Yoon, and S. R. Maeng. An adaptive sequential prefetching scheme in shared-memory multiprocessors. In the Proceedings of the International Conference on Parallel Processing, pages 306-313, 1997.