Scheduling and partitioning for multiple loop nests

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2001, Pages 183-188

  Wang, Zhong ^a   Zhuge, Qingfeng ^b   Sha, Edwin H M ^b  

^a University of Notre Dame   (United States)

^b The University of Texas at Dallas   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTATION THEORY; DIGITAL SIGNAL PROCESSING; MATHEMATICAL MODELS; SCHEDULING;

MULTIPLE LOOP NESTS;

PARALLEL PROCESSING SYSTEMS;

EID: 0034785161     PISSN: 10801820     EISSN: None     Source Type: Journal    
DOI: 10.1145/500001.500042     Document Type: Article

References (10)

1. Loop scheduling and partitions for hiding memory latencies
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4. Fusion of loops for parallelism and locality
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6. Achieving full parallelism using multi-dimensional retiming
7. Scheduling of uniform multi-dimensional systems under resource constraints
8. (pen)-ultimate tiling
9. On uniformization of affine dependence algorithms
10. Optimal two level partitioning and loop scheduling for hiding memory latency for dsp applications