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Volumn , Issue , 1995, Pages 338-349
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Stage scheduling: a technique to reduce the register requirements of a modulo schedule
a
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Author keywords
[No Author keywords available]
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Indexed keywords
CODES (SYMBOLS);
COMPUTATIONAL COMPLEXITY;
COMPUTER ARCHITECTURE;
HEURISTIC PROGRAMMING;
ITERATIVE METHODS;
PARALLEL PROCESSING SYSTEMS;
PIPELINE PROCESSING SYSTEMS;
PROGRAM COMPILERS;
SCHEDULING;
STORAGE ALLOCATION (COMPUTER);
HIGH PERFORMANCE CODES;
INSTRUCTION LEVEL PARALLELISM;
ITERATIONS;
LOOP SCHEDULING;
REGISTER REQUIREMENTS;
REGISTER SENSITIVE MODULO SCHEDULING;
SOFTWARE PIPELINING;
SUPERSCALAR;
VERY LONG INSTRUCTION WORD;
SOFTWARE ENGINEERING;
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EID: 0029487619
PISSN: 10724451
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (49)
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References (25)
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