A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified ISOnm logic process for high-density on-chip memory applications

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 355-358

  Somasekhar, Dinesh ^a   Lu, Shih Lien ^a   Bloechel, Bradley ^a   Dermer, Greg ^a   Lai, Konrad ^a   Borkar, Shekhar ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

10MB PLANAR IT-1C DRAM CHIPS; 6T SRAM CACHE; HIGH-DENSITY ON-CHIP; POWER DENSITY;

BANDWIDTH; BUFFER STORAGE; DYNAMIC RANDOM ACCESS STORAGE; LOGIC DEVICES; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE;

MOS CAPACITORS;

EID: 33749181377     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541633     Document Type: Conference Paper

References (6)

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