Trends in low-voltage embedded-RAM technology

2002 23rd International Conference on Microelectronics, MIEL 2002 - Proceedings

Volumn 2, Issue , 2002, Pages 497-501

  Itoh, Kiyoo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; LEAKAGE CURRENTS; MICROELECTRONICS; STORAGE ALLOCATION (COMPUTER); SYSTEM-ON-CHIP;

ACTIVE MODE; EMBEDDED RAMS; GATE OXIDE; LOW VOLTAGE OPERATION; LOW-VOLTAGE; NON-VOLATILE; SIGNAL CHARGE; SOC ARCHITECTURE;

STATIC RANDOM ACCESS STORAGE;

EID: 0242509351     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MIEL.2002.1003306     Document Type: Conference Paper

References (16)

1. K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001.
2. K. Itoh and H.Mizuno, "Low-Voltage Embedded-RAM Technology: Present and Future, "Proc. of the 11th IFIP Int. Conference on Very Large Scale Integration, pp.393-398, Dec.2001.
3. O. Takahashi et al., "1GHz Fully Pipelined 3.7ns Address Access Time 8kx1 024 Embedded DRAM Macro, "ISSCC2000, pp.396-397.
4. J. Barth et al., "A 300MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write, "ISSCC2002, pp.156-157.
5. T. Inukai et al., "Suppression of Stand-by Tunnel Current in Ultra-Thin Gate Oxide MOSFETs, "SSDM1999, pp.264-265.
6. M. Miyazaki et al., "A 175 mV Multiply-Accumulate Unit usin g an Adaptive supply voltage and Body Bias (ASB) Architecture, "ISSCC2002, pp.58-59.
7. A. Keshavarzi et al., "Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt CMOS ICs, "ISLPED2001, pp.207-212.
8. A. Alvandpour et al., "A Conditional Keeper Technique for Sub-0.13-m Wide Dynamic Gates, "2001 Symp. on VLSI Circuits, pp.29-30.
9. E.Ibe, "Current and Future Trend on Cosmic-Ray-Neutron Induced Single Event Upset at the Ground down to 0.1-Micron-Devices, "The Svedberg Laboratory Workshop on Applied physics, Uppsala, May 3, 2001.
10. S. Miyano and M. Takahashi, "Embedded DRAM SOCs and Its Application for MPEG4 Codec LSIs, "Proceedings of VLSI CIRCUITS SHORT COURSE, pp.101-121, June 2001.
11. W. Leung et al., "The Ideal SoC Memory: 1T-SRAM, "13th Annual IEEE Int. ASIC/SOC Conference, Sept.2000.
12. K. Takada et al., "A 16Mb 400MHz Loadless CMOS Four-Transistor SRAM Macro, "ISSCC2000, pp.264-265.
13. K. Itoh et a l., "A Deep Sub-V, Single Power-Supply SRAM Cell with Multi-Vt, Boosted Storage Node and Dynamic Load, "1996 Symp. on VLSI Circuits, pp.132-133.
14. International Technology Roadmap for Semiconductors, 2001 Edition, System Driver (Fig.12)
15. P.K. Naji et al., "A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM, "ISSCC2001, pp.122-123.
16. M.Gill et al., "Ovonic Unified Memory-A High-Performance Nonvolatile Memory Technology for Stand-Alone Memory and Embedded Applications, "ISSCC2002, pp.202-203.