A compact eFUSE programmable array memory for SOI CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 72-73

  Safran, John ^a   Leslie, Alan ^a   Fredeman, Gregory ^a   Kothandaraman, Chandrasekharan ^a   Cestero, Alberto ^a   Chen, Xiang ^a   Rajeevakumar, Raj ^a   Kim, Deok Kee ^a   Li, Yan Zun ^a   Moy, Dan ^a   Robson, Norman ^a   Kirihata, Toshiaki ^a   Iyer, Subramanian ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

CMOS; Electrical fuse; OTPROM

Indexed keywords

COSTS; ROM; STORAGE ALLOCATION (COMPUTER); VLSI CIRCUITS;

ASYMMETRICAL SCALING; ELECTRICAL FUSE; PROGRAMMABLE ARRAY MEMORY;

CMOS INTEGRATED CIRCUITS;

EID: 39749182772     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342770     Document Type: Conference Paper

References (5)

1. C. Kothandaraman, et. al., "Electrically Programmable Fuse (eFUSE) Using Electromigration in Suicides", IEEE EDL, Sep. 2002, pp. 523-525.
2. H. Cha, et. al., "A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller", IEEE JSSC, Sep. 2006, pp. 2115-2124.
3. D. Anand, el al., "An on-chip self-repair calculation and fusing methodology", IEEE Design & Test of Computers, Sep-Oct. 2003, pp. 67-75.
4. 2 Electrical Fuse for 90nm Technology", 2006 IRPS Proceedings, pp. 392-397.
5. J. Barth et. al., "A 500MHr Random Cycle, 1.5ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier", 2007ISSCC (in press, to be presented).