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0037347054
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Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages
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March
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Chabini, N.; Chabini, L; Aboulhamid, E.M.; Savaria, Y.; "Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 22, Issue 3, March 2003 Page(s):346-351.
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Chabini, N.1
Chabini, L.2
Aboulhamid, E.M.3
Savaria, Y.4
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Energy minimization using multiple supply voltages
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Dec.
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Jui-Ming Chang; Pedram, M.; "Energy minimization using multiple supply voltages", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 5, Issue 4, Dec. 1997 Page(s):436-443.
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Chang, J.-M.1
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Design of low-power domino circuits using multiple supply voltages
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2-5 Sept. vol.2
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Shang-Jyh Shieh; Jinn-Shyan Wang; "Design of low-power domino circuits using multiple supply voltages", The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001. ICECS 2001. Volume 2, 2-5 Sept. 2001 Page(s):711-714 vol.2
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The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001. ICECS 2001
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Shieh, S.-J.1
Wang, J.-S.2
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0036683762
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Low power CMOS level shifters by bootstrapping technique
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1 Aug
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Tan, S.C.; Sun, X.W.; "Low power CMOS level shifters by bootstrapping technique", Electronics Letters, Volume: 38, Issue: 16, 1 Aug 2002, Pages:876-878.
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Electronics Letters
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Tan, S.C.1
Sun, X.W.2
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5
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0034849202
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Level shifters for high-speed 1 v to 3.3 v interfaces in a 0.13um Cu-interconnection/low-k CMOS technology
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18-20 April
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Wen-Tai Wang; Ming-Dou Ker; Mi-Chang Chiang; Chung-Hui Chen; "Level shifters for high-speed 1 V to 3.3 V interfaces in a 0.13um Cu-interconnection/ low-k CMOS technology", International Symposium on VLSI Technology, Systems, and Applications, 18-20 April 2001, Pages:307-310.
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International Symposium on VLSI Technology, Systems, and Applications
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Wang, W.-T.1
Ker, M.-D.2
Chiang, M.-C.3
Chen, C.-H.4
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6
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High performance level conversion for dual VDD design
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Sept.
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Kulkarni, S.H.; Sylvester, D.; "High performance level conversion for dual VDD design", IEEE Transactions on Very Large Scale Integration (VLSI) SystemsVolume 12, Issue 9, Sept. 2004 Page(s):926-936.
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Kulkarni, S.H.1
Sylvester, D.2
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7
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0042635592
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Pushing ASIC performance in a power envelope
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2-6 June
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Puri, R.; Stok, L.; Cohn, J.; Kung, D.; Pan, D.; Sylvester, D.; Srivastava, A.; Kulkarni, S.; "Pushing ASIC performance in a power envelope", Proceedings of Design Automation Conference, 2-6 June 2003, Pages: 788-793.
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(2003)
Proceedings of Design Automation Conference
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Puri, R.1
Stok, L.2
Cohn, J.3
Kung, D.4
Pan, D.5
Sylvester, D.6
Srivastava, A.7
Kulkarni, S.8
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