Integrating III-V on silicon for future transistor applications

Solid State Technology

Volumn 51, Issue 7, 2008, Pages 30-36

  Chau, Robert ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; INTEGRATION; LITHOGRAPHY; NONMETALS; TRANSISTORS;

CHANNEL MATERIALS; CMOS TRANSISTORS; DEVICE PERFORMANCES; ELECTRONIC MATERIALS; FUTURE TECHNOLOGIES; NON-SILICON MATERIALS; SILICON SUBSTRATES; TRANSISTOR APPLICATIONS;

SILICON;

EID: 49149130027     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (13)

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9. W.A. de Heer et al., "Pionics: the Emerging Science and Technology of Graphene-based Nanoelectronics," IEDM Technical Digest, 2007, pp. 199-202.
10. R. Chau, "III-V on Silicon for Future High Speed and Ultra-Low Power Digital Applications: Challenges and Opportunities," Compound Semiconductor Mantech, Digest of Papers, 2008, pp. 15-18.
11. J.B. Boos et al., "High mobility p-channel HFETs using strained Sb-based materials," Electronics Letters, Vol. 43, No. 15, July 2007.
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13. R. Chau et al., "Integrated Nanoelectronics for the Future," Nature Materials, Vol. 6, Nov. 2007, pp. 810-812.