-
1
-
-
48649100397
-
-
2005 Edition, Online, Available
-
ITRS, International Technology Roadmap for Semiconductors 2005 Edition, 2005. [Online]. Available: http://www.itrs.net/Links/ 2005ITRS/Home2005.htm
-
(2005)
-
-
-
2
-
-
0033688763
-
Low power and high performance design challenges in future technologies
-
New York
-
V. De and S. Borkar, "Low power and high performance design challenges in future technologies," in Proc.10th GLSVLSI, New York, 2000, pp. 1-6.
-
(2000)
Proc.10th GLSVLSI
, pp. 1-6
-
-
De, V.1
Borkar, S.2
-
3
-
-
33947265310
-
Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs
-
Dec
-
G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov, "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs," IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3063-3070, Dec. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.12
, pp. 3063-3070
-
-
Roy, G.1
Brown, A.R.2
Adamu-Lema, F.3
Roy, S.4
Asenov, A.5
-
4
-
-
36248947996
-
Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture
-
Nov
-
A. R. Brown, G. Roy, and A. Asenov, "Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture," IEEE Trans. Electron Devices, vol. 54, no. 11, pp. 3056-3003, Nov. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.11
, pp. 3056-3003
-
-
Brown, A.R.1
Roy, G.2
Asenov, A.3
-
5
-
-
0037004304
-
High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide
-
Dec
-
S. Inaba et al., "High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2263-2270, Dec. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.12
, pp. 2263-2270
-
-
Inaba, S.1
-
6
-
-
48649096822
-
-
NanoCMOS eScience Pilot Project, Online, Available
-
NanoCMOS eScience Pilot Project. [Online]. Available: http:// www.nanocmos.ac.uk
-
-
-
-
7
-
-
48649107795
-
-
A. Asenov, A. R. Brown, B. Cheng, J. R. Watling, G. Roy, and C. Alexander, Nanotechnology for Electronic Materials and Devices. New York: Springer-Verlag, 2006, ch. Simulation of nano-CMOS devices: From atoms to architecture.
-
A. Asenov, A. R. Brown, B. Cheng, J. R. Watling, G. Roy, and C. Alexander, Nanotechnology for Electronic Materials and Devices. New York: Springer-Verlag, 2006, ch. Simulation of nano-CMOS devices: From atoms to architecture.
-
-
-
-
8
-
-
48649092640
-
-
Synopsys, Mountain View, CA, Sep, 2004.09 edition
-
Taurus Process and Device - Users Guide, Synopsys, Mountain View, CA, Sep. 2004. 2004.09 edition.
-
(2004)
Taurus Process and Device - Users Guide
-
-
-
9
-
-
0033281305
-
Monte Carlo modeling of threshold variation due to dopant fluctuations
-
D. Frank, Y. Taur, M. Ieong, and H.-S. P. Wong, "Monte Carlo modeling of threshold variation due to dopant fluctuations," in VLSI Symp. Tech. Dig., 1999, pp. 169-170.
-
(1999)
VLSI Symp. Tech. Dig
, pp. 169-170
-
-
Frank, D.1
Taur, Y.2
Ieong, M.3
Wong, H.-S.P.4
-
11
-
-
48649091785
-
High performance CMOS variability in the 65 nm regime and beyond
-
S. Nassif, K. Bernstein, D. J. Frank, A. Gattiker, W. Haensch, B. L. Ji, E. Nowak, D. Pearson, and N. J. Rohrer, "High performance CMOS variability in the 65 nm regime and beyond," in IEDM Tech. Dig., 2007, pp. 569-571.
-
(2007)
IEDM Tech. Dig
, pp. 569-571
-
-
Nassif, S.1
Bernstein, K.2
Frank, D.J.3
Gattiker, A.4
Haensch, W.5
Ji, B.L.6
Nowak, E.7
Pearson, D.8
Rohrer, N.J.9
-
12
-
-
33845385377
-
-
Univ. Pennsylvania, Philadelphia, PA, Tech. Rep, Dec
-
J. Heinrich, "A Guide to the Pearson Type IV Distribution," Univ. Pennsylvania, Philadelphia, PA, Tech. Rep., Dec. 2004.
-
(2004)
A Guide to the Pearson Type IV Distribution
-
-
Heinrich, J.1
|