Cost-efficient SHA hardware accelerators

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 8, 2008, Pages 999-1008

  Chaves, Ricardo ^a,b,c   Kuzmanov, Georgi ^a,c   Sousa, Leonel ^a,b   Vassiliadis, Stamatis ^a,c  

^a IEEE

^b INSTITUTO SUPERIOR TÉCNICO   (Portugal)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Crytography; Field programmable gate array (FPGA); Hardware implementation; Hash functions; Secure Hash Algorithm (SHA)

Indexed keywords

FUNCTIONS;

COST-EFFICIENT; CRITICAL PATHS; CRYTOGRAPHY; FIELD-PROGRAMMABLE GATE ARRAY (FPGA); HARDWARE ACCELERATORS; HARDWARE IMPLEMENTATION; HARDWARE IMPLEMENTATIONS; HASH FUNCTIONS; RE-UTILIZATION; SECURE HASH ALGORITHM (SHA); SECURE HASH ALGORITHM); SOFTWARE IMPLEMENTATIONS; XILINX VIRTEX;

HARDWARE;

EID: 48349138632     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2000450     Document Type: Article

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