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Volumn 4249 LNCS, Issue , 2006, Pages 298-310

Improving SHA-2 hardware implementations

Author keywords

Cryptography; FPGA; Hash functions; SHA 2 (256, 512)

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; PUBLIC KEY CRYPTOGRAPHY; SOFTWARE PROTOTYPING; THROUGHPUT;

EID: 33750729555     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11894063_24     Document Type: Conference Paper
Times cited : (65)

References (16)
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    • Dadda, L.1    Macchetti, M.2    Owen, J.3
  • 3
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    • An ASIC design for a high speed implementation of the hash, function SHA-256 (384, 512)
    • Garrett, D., Lach, J., Zukowski, C.A., eds., ACM
    • Dadda, L., Macchetti, M., Owen, J.: An ASIC design for a high speed implementation of the hash, function SHA-256 (384, 512). In Garrett, D., Lach, J., Zukowski, C.A., eds.: ACM Great Lakes Symposium on VLSI, ACM (2004) 421-425
    • (2004) ACM Great Lakes Symposium on VLSI , pp. 421-425
    • Dadda, L.1    Macchetti, M.2    Owen, J.3
  • 4
    • 84945300922 scopus 로고    scopus 로고
    • Comparative analysis of the hardware implementations of hash functions SHA-1 and SHA-512
    • Chan, A.H., Gligor, V.D., eds.: ISC, Springer
    • Grembowski, T., Lien, R., Gaj, K., Nguyen, N., Bellows, P., Flidr, J., Lehman, T., Schott, B.: Comparative analysis of the hardware implementations of hash functions SHA-1 and SHA-512. In Chan, A.H., Gligor, V.D., eds.: ISC. Volume 2433 of Lecture Notes in Computer Science., Springer (2002) 75-89
    • (2002) Lecture Notes in Computer Science , vol.2433 , pp. 75-89
    • Grembowski, T.1    Lien, R.2    Gaj, K.3    Nguyen, N.4    Bellows, P.5    Flidr, J.6    Lehman, T.7    Schott, B.8
  • 6
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    • Implementation of the SHA-2 hash family standard using FPGAs
    • Sklavos, N., Koufopavlou, O.: Implementation of the SHA-2 hash family standard using FPGAs. The Journal of Supercomputing 31 (2005) 227248
    • (2005) The Journal of Supercomputing , vol.31 , pp. 227248
    • Sklavos, N.1    Koufopavlou, O.2
  • 7
    • 79955162305 scopus 로고    scopus 로고
    • An FPGA based SHA-256 processor
    • Glesner, M., Zipf, P., Renovell, M., eds.: FPL. Springer
    • Ting, K.K., Yuen, S.C.L., Lee, K.H., Leong, P.H.W.: An FPGA Based SHA-256 Processor. In Glesner, M., Zipf, P., Renovell, M., eds.: FPL. Volume 2438 of Lecture Notes in Computer Science., Springer (2002) 577-585
    • (2002) Lecture Notes in Computer Science , vol.2438 , pp. 577-585
    • Ting, K.K.1    Yuen, S.C.L.2    Lee, K.H.3    Leong, P.H.W.4
  • 9
    • 33646401086 scopus 로고    scopus 로고
    • Optimizing SHA-1 hash function for high throughput with a partial unrolling study
    • Paliouras, V., Vounckx, J., Verkest, D., eds.: PATMOS. Springer
    • Michail, H.E., Kakarountas, A.P., Selimis, G.N., Goutis, C.E.: Optimizing SHA-1 hash function for high throughput with a partial unrolling study. In Paliouras, V., Vounckx, J., Verkest, D., eds.: PATMOS. Volume 3728 of Lecture Notes in Computer Science., Springer (2005) 591-600
    • (2005) Lecture Notes in Computer Science , vol.3728 , pp. 591-600
    • Michail, H.E.1    Kakarountas, A.P.2    Selimis, G.N.3    Goutis, C.E.4
  • 10
    • 85052691556 scopus 로고
    • FIPS 180-1. Technical report, National Institute of Standards and Technology
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  • 12
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    • Omitted due to the blind review submission
    • (Omitted due to the blind review submission)
  • 16
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    • A 1 Gbit/s partially unrolled architecture of hash functions SHA-1 and SHA-512
    • Lien, R., Grembowski, T., Gaj, K.: A 1 Gbit/s partially unrolled architecture of hash functions SHA-1 and SHA-512. In: CT-RSA. (2004) 324-338
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.