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1
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3042615299
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The design of a high speed ASIC unit for the hash function SHA-256 (384, 512)
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IEEE Computer Society
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Dadda, L., Macchetti, M., Owen, J.: The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512). In: DATE, IEEE Computer Society (2004) 70-75
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Dadda, L.1
Macchetti, M.2
Owen, J.3
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3
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2942671000
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An ASIC design for a high speed implementation of the hash, function SHA-256 (384, 512)
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Garrett, D., Lach, J., Zukowski, C.A., eds., ACM
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Dadda, L., Macchetti, M., Owen, J.: An ASIC design for a high speed implementation of the hash, function SHA-256 (384, 512). In Garrett, D., Lach, J., Zukowski, C.A., eds.: ACM Great Lakes Symposium on VLSI, ACM (2004) 421-425
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Dadda, L.1
Macchetti, M.2
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4
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84945300922
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Comparative analysis of the hardware implementations of hash functions SHA-1 and SHA-512
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Grembowski, T., Lien, R., Gaj, K., Nguyen, N., Bellows, P., Flidr, J., Lehman, T., Schott, B.: Comparative analysis of the hardware implementations of hash functions SHA-1 and SHA-512. In Chan, A.H., Gligor, V.D., eds.: ISC. Volume 2433 of Lecture Notes in Computer Science., Springer (2002) 75-89
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Implementation of the SHA-2 hash family standard using FPGAs
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Sklavos, N.1
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7
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An FPGA based SHA-256 processor
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Glesner, M., Zipf, P., Renovell, M., eds.: FPL. Springer
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Ting, K.K., Yuen, S.C.L., Lee, K.H., Leong, P.H.W.: An FPGA Based SHA-256 Processor. In Glesner, M., Zipf, P., Renovell, M., eds.: FPL. Volume 2438 of Lecture Notes in Computer Science., Springer (2002) 577-585
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Ting, K.K.1
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Leong, P.H.W.4
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8
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Optimisation of the SHA-2 family of hash functions on FPGAs
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McEvoy, R.P., Crowe, F.M., Murphy, C.C., Marnane, W.P.: Optimisation of the SHA-2 family of hash functions on FPGAs. IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06) (2006) 317-322
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McEvoy, R.P.1
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Murphy, C.C.3
Marnane, W.P.4
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9
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33646401086
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Optimizing SHA-1 hash function for high throughput with a partial unrolling study
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Paliouras, V., Vounckx, J., Verkest, D., eds.: PATMOS. Springer
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Michail, H.E., Kakarountas, A.P., Selimis, G.N., Goutis, C.E.: Optimizing SHA-1 hash function for high throughput with a partial unrolling study. In Paliouras, V., Vounckx, J., Verkest, D., eds.: PATMOS. Volume 3728 of Lecture Notes in Computer Science., Springer (2005) 591-600
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Omitted due to the blind review submission
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(Omitted due to the blind review submission)
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13
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The Molen polymorphic processor
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Vassiliadis, S., Wong, S., Gaydadjiev, G.N., Berteis, K., Kuzmanov, G., Panainte, E.M.: The Molen polymorphic processor. IEEE Transactions on Computers (2004) 1363-1375
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Vassiliadis, S.1
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Gaydadjiev, G.N.3
Berteis, K.4
Kuzmanov, G.5
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14
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0037744606
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On the hardware implementation of the SHA-2 (256,384,512) hash functions
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Sklavos, N., Koufopavlou, O.: On the hardware implementation of the SHA-2 (256,384,512) hash functions, proc. of IEEE International symposium on Circuits and systems (ISCAS 2003) (2003) 25-28
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Sklavos, N.1
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A 1 Gbit/s partially unrolled architecture of hash functions SHA-1 and SHA-512
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