A novel partial bitstream merging methodology accelerating xilinx virtex-ii FPGA based RP system setup

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 701-704

  Bieser, Carsten ^a   Bahlinger, Martin ^a   Heinz, Matthias ^a   Stops, Christian ^a   Mueller Glaser, Klaus D ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENT ENGINEERING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; JOB ANALYSIS; PINCH EFFECT; PROCESS ENGINEERING; PRODUCT DEVELOPMENT; RAPID PROTOTYPING;

BIT STREAM (BS); CONFIGURABILITY; DESIGN TIME; ELECTRONIC DESIGNS; ENGINEERING PROCESSES; FIELD PROGRAMMABLE LOGIC (FPL); INTERNATIONAL CONFERENCES; RAPID PROTOTYPING (RP); RE PROGRAMMABILITY; RP SYSTEMS; TURN-AROUND; XILINX VIRTEX II FPGA;

MERGING;

EID: 46249095550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311294     Document Type: Conference Paper

References (11)

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