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Volumn , Issue , 2007, Pages 217-222

Detecting malicious logic through structural checking

Author keywords

[No Author keywords available]

Indexed keywords

SECURITY BREACHES; SYSTEM FAILURES; SYSTEM RESOURCES; TECHNICAL CONFERENCES;

EID: 48049105514     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TPSD.2007.4380384     Document Type: Conference Paper
Times cited : (17)

References (40)
  • 3
    • 48049101766 scopus 로고    scopus 로고
    • available February 2007
    • Wikipedia: http://en.wikipedia.org/wiki/Formal_equivalence_checking (available February 2007).
  • 8
    • 21244493661 scopus 로고    scopus 로고
    • M. N. Mneimneh and K. A. Sakallah, Principles of Sequential-Equivalence Verification, IEEE Design & Test of Computers, 22,/3, May 2005.
    • M. N. Mneimneh and K. A. Sakallah, "Principles of Sequential-Equivalence Verification," IEEE Design & Test of Computers, Vol. 22,/3, May 2005.
  • 11
    • 0035394168 scopus 로고    scopus 로고
    • Applied Boolean Equivalence Verification and RTL Static Sign-off
    • Jul
    • H. Foster, "Applied Boolean Equivalence Verification and RTL Static Sign-off," IEEE Design & Test of Computers, Vol. 18/4, Jul. 2002.
    • (2002) IEEE Design & Test of Computers , vol.18 , Issue.4
    • Foster, H.1
  • 13
    • 0028203071 scopus 로고
    • Automated Verification of Behavioral Equivalence for Microprocessors
    • Jan
    • F. Corella, "Automated Verification of Behavioral Equivalence for Microprocessors," IEEE Transactions on Computers, Vol. 43/1, Jan. 1994.
    • (1994) IEEE Transactions on Computers , vol.43 , Issue.1
    • Corella, F.1
  • 14
    • 0008648148 scopus 로고    scopus 로고
    • Formal Verification of an Advanced Pipeline Machine,
    • Ph.D. Dissertation, University of Texas at Austin, Dec
    • J. Sawada, "Formal Verification of an Advanced Pipeline Machine," Ph.D. Dissertation, University of Texas at Austin, Dec. 1999.
    • (1999)
    • Sawada, J.1
  • 15
    • 0032630203 scopus 로고    scopus 로고
    • Verifying lhe FM9801 Microarchitecture
    • May
    • W. A. Hunt and J. Sawada, "Verifying lhe FM9801 Microarchitecture, " IEEE Micro, Vol. 19/3, May 1999.
    • (1999) IEEE Micro , vol.19 , Issue.3
    • Hunt, W.A.1    Sawada, J.2
  • 17
    • 33645601064 scopus 로고    scopus 로고
    • CMC: A Model Checker for Network Protocol Implementations,
    • Ph.D. Dissertation, Stanford University, Feb
    • M. Musuvathi, "CMC: A Model Checker for Network Protocol Implementations," Ph.D. Dissertation, Stanford University, Feb. 2004.
    • (2004)
    • Musuvathi, M.1
  • 19
    • 0001550560 scopus 로고
    • Formal Hardware Verification Methods: A Survey
    • A. Gupta, "Formal Hardware Verification Methods: A Survey," Formal Methods in System Design, Vol. 1, pp. 151-238, 1992.
    • (1992) Formal Methods in System Design , vol.1 , pp. 151-238
    • Gupta, A.1
  • 21
    • 0022769976 scopus 로고
    • Graph-based algorithms for Boolean function manipulation
    • R. E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Transactions on Computers, Vol. 35/8, pp. 677-691, 1986.
    • (1986) IEEE Transactions on Computers , vol.35 , Issue.8 , pp. 677-691
    • Bryant, R.E.1
  • 24
    • 84958599158 scopus 로고    scopus 로고
    • From asymmetry to full symmetry: New techniques for symmetry reduction in model checking
    • Correct Hardware Design and Verification Methods CHARME, Springer-Verlag, New York, pp
    • E. Emerson, and R. Trefler, "From asymmetry to full symmetry: New techniques for symmetry reduction in model checking," Correct Hardware Design and Verification Methods (CHARME), Lecture Notes in Computer Science, Vol. 1703, Springer-Verlag, New York, pp. 142-156, 1999.
    • (1999) Lecture Notes in Computer Science , vol.1703 , pp. 142-156
    • Emerson, E.1    Trefler, R.2
  • 26
    • 0030215698 scopus 로고    scopus 로고
    • Condensed state spaces for symmetrical colored petri nets
    • K. Jensen, "Condensed state spaces for symmetrical colored petri nets," Formal Methods in System Design 9, Vol. 1/2, pp. 7-40, 1996.
    • (1996) Formal Methods in System Design 9 , vol.1-2 , pp. 7-40
    • Jensen, K.1
  • 28
    • 85010991128 scopus 로고
    • All from one, one from all: On model checking using representatives
    • th International Conference on Computer Aided Verification, Springer-Verlag, New York, pp
    • th International Conference on Computer Aided Verification, Lecture Notes in Computer Science, Vol. 697, Springer-Verlag, New York, pp. 409-423, 1993.
    • (1993) Lecture Notes in Computer Science , vol.697 , pp. 409-423
    • Peled, D.1
  • 29
    • 0032672388 scopus 로고    scopus 로고
    • Refining model checking by abstract interpretation
    • P. Cousot, and R. Cousot, "Refining model checking by abstract interpretation," Automated Software Engineering, Vol. 6, pp. 69-95, 1999.
    • (1999) Automated Software Engineering , vol.6 , pp. 69-95
    • Cousot, P.1    Cousot, R.2
  • 30
    • 48049119549 scopus 로고    scopus 로고
    • D. E. Long, Model checking, abstraction and compositional verification, Ph.D. dissertation, School of Computer Science, Carnegie Mellon University, Pittsburgh, Pa. CMU-CS-93-178, 1993.
    • D. E. Long, "Model checking, abstraction and compositional verification," Ph.D. dissertation, School of Computer Science, Carnegie Mellon University, Pittsburgh, Pa. CMU-CS-93-178, 1993.
  • 37
    • 48049104184 scopus 로고    scopus 로고
    • available February 2007
    • Wikipedia: http://en.wikbedia.org/wiki/Theorem_proving (available February 2007).
  • 38
    • 0003878157 scopus 로고
    • Ph.D. Dissertation, Technical report ICSCA-CMP-47, University of Texas at Austin
    • W. A. Hunt, "FM8501: A verified microprocessor," Ph.D. Dissertation, Technical report ICSCA-CMP-47, University of Texas at Austin, 1985.
    • (1985) FM8501: A verified microprocessor
    • Hunt, W.A.1
  • 39
    • 2442496292 scopus 로고
    • The mechanical verification of a microprocessor design
    • D. Borrione, editor, North Holland, Amsterdam
    • W. A. Hunt, "The mechanical verification of a microprocessor design," In D. Borrione, editor, From HDL Description to Guaranteed Correct Circuit Designs, pp. 89-129, North Holland, Amsterdam, 1987.
    • (1987) From HDL Description to Guaranteed Correct Circuit Designs , pp. 89-129
    • Hunt, W.A.1
  • 40
    • 48049084349 scopus 로고    scopus 로고
    • A Hardware Threat Modeling Concept for Trustable Integrated Circuits
    • to appear in, April
    • J. Di and S. C. Smith, "A Hardware Threat Modeling Concept for Trustable Integrated Circuits," to appear in IEEE Region 5 Technical Conference, April 2007.
    • (2007) IEEE Region 5 Technical Conference
    • Di, J.1    Smith, S.C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.