Incremental CTL model checking using BDD subsetting

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 457-462

  Pardo, Abelardo ^a   Hachtel, Gary D ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b UNIVERSITY OF COLORADO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; BOOLEAN FUNCTIONS; ALGORITHMS; APPROXIMATION THEORY; COMPUTATIONAL METHODS; DECISION THEORY; ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; MATHEMATICAL MODELS;

AUTOMATIC ABSTRACTIONS; COMPUTATIONAL RESOURCES; CONSERVATIVE MODELING; CTL MODEL-CHECKING; UNDER-APPROXIMATION;

MODEL CHECKING; LOGIC CIRCUITS;

BINARY DECISION DIAGRAMS (BDD); COMPLEMENTARY TRANSISTOR LOGIC (CTL) CIRCUITS;

EID: 0031645531     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277171     Document Type: Conference Paper

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