An all-digital phase-locked loop for high-speed clock generation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2002, Pages

  Chung, Ching Che ^a   Lee, Chen Yi ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DETECTOR CIRCUITS; DIGITAL FILTERS; FREQUENCY DIVIDING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; JITTER; OSCILLATORS (ELECTRONIC); TIMING CIRCUITS;

ALL DIGITAL PHASE LOCKED LOOP; DIGITAL CONTROLLED OSCILLATORS; HIGH-SPEED CLOCK GENERATION; STANDARD CELL LIBRARY;

PHASE LOCKED LOOPS;

EID: 0036292579     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. An all-digital phase-locked loop with 50-cycle lock time suitable for high performance microprocessors
2. The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock
3. An all-digital phase-locked loop (ADPLL)-based clock recovery circuit
4. Fully integrated standard cell digital PLL
5. A novel structure for portable digitally controlled oscillator