Power estimation of time variant SoCs with TAPES

Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007

Volumn , Issue , 2007, Pages 261-264

  Lankes, Andreas ^a   Wild, Thomas ^a   Zeppenfeld, Johannes ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE EXPLORATIONS; DESIGN PROCESSES; DESIGN SPACES; DESIGN TOOLS; EVALUATION CRITERIONS; NETWORK PROCESSORS; POWER CONSUMPTIONS; POWER ESTIMATIONS; POWER MINIMIZATIONS; RUN TIMES; SYSTEM SIMULATORS; SYSTEMS ON CHIPS; TIME VARIANTS;

COMPUTER ARCHITECTURE; DESIGN; ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS;

ARCHITECTURAL DESIGN;

EID: 47749153356     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2007.4341478     Document Type: Conference Paper

References (14)

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