TAPES-Trace-based architecture performance evaluation with SystemC

Design Automation for Embedded Systems

Volumn 10, Issue 2-3, 2005, Pages 157-179

  Wild, Thomas ^a   Herkersdorf, Andreas ^a   Lee, Gyoo Yeong ^b  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b Kangwon National University   (South Korea)

Author keywords

Architecture exploration; Performance evaluation; SystemC; Trace driven simulation; Transaction level modeling

Indexed keywords

COMPUTER APPLICATIONS; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; LARGE SCALE SYSTEMS; PROGRAM PROCESSORS;

ARCHITECTURE EXPLORATION; PERFORMANCE EVALUATION; SYSTEMC; TRACE-DRIVEN SIMULATION; TRANSACTION LEVEL MODELING;

COMPUTER ARCHITECTURE;

EID: 33749010321     PISSN: 09295585     EISSN: 15728080     Source Type: Journal    
DOI: 10.1007/s10617-006-9589-4     Document Type: Article

References (19)

1. Balarin, F. et al. Hardware-Software Co-Design of Embedded Systems: The Polis Approach. Kluwer Academic Publishers, 1997.
2. Balarin, F. et al. Metropolis, An Integrated Electronic System Design Environment. IEEE Computer, April 2003.
3. Buck, J. et al. Polemy: A Framework for Simulating and Prototyping Heterogeneous Systems. Int'l J. Computer Simulation, Apr. 1994.
4. Cai, L. and D. Gajski. Transaction Level Modeling: An Overview, CODES+ISSS, 2003.
5. Donlin, A. Transaction Level Modeling: Flows and Use Models, CODES+ISSS, 2004.
6. Grötker, T., S. Liao, G. Martin, and S. Swan. System Design with SystemC, Kluwer Academic Publishers, Boston, May 2002.
7. Henia, R., A. Hamann, M. Jersak, R. Racu, K. Richter, and R. Ernst. System Level Performance Analysis - the SymTA/S Approach. IEE Proc.-Comput. Tech., March 2005.
8. Keutzer, K., et al. System Level Design: Orthogonalization of Concerns and Platform-based Design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 19, 2000.
9. Kohler, E. et al. The Click Modular Router. ACM Trans. on Computer Systems, 18(3), 2000.
10. Lahiri, A., A. Raghunathan, and S. Dey. Fast Performance Analysis of Bus-Based System-On-Chip Communication Architectures, ICCAD, 1999.
11. Lieverse, P., P. van der Wolf, and E. Deprettere. A Trace Transformation Technique for Communication Refinement, CODES, 2001.
12. Ohlendorf, R., A. Herkersdorf, and T. Wild. FlexPath NP-A Network Processor Concept with Application-Driven Flexible Processing Paths, CODES+1SSS, 2005.
13. Paulin, P., C. Pilkington, and E. Bensoudane. StepNP: A System-Level Exploration Platform for Network Processors. IEEE Design&Test of Computers, Nov.-Dec. 2002.
14. Prete, A., G. Prina, and L. Ricciardi. A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems. IEEE Trans. Parallel and Distributed Systems, 6(9), 1995.
15. Ramaswamy, R. and T. Wolf. PacketBench: A Tool for Workload Characterization of Network Processing. IEEE Workshop on Workload Characterization, Oct. 2003.
16. Sherman, S.W. and J.C. Browne. Trace Driven Modeling: Review and Overview. In Proceeding Symp. On Simulation of Computer Systems, 1973.
17. Sonntag, S., M. Gries, and C. Sauer. SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC. In Proceeding Emb. Comp. Systems: Architectures, Modeling, and Simulation (SAMOS), 2005.
18. SystemC homepage, http://www.systemc.org.
19. Thiele, L. and E. Wandeler. Performance Analysis of Distributed Embedded Systems, in R. Zurawski (ed.), Embedded Systems Handbook, CRC Press, 2005.