RF/wireless interconnects in future on-chip and board-level clock distribution network

2007 IEEE International Conference on Electro/Information Technology, EIT 2007

Volumn , Issue , 2007, Pages 542-545

  Roy, Abinash ^a,b   Chowdhury, Masud H ^a,b  

^a IEEE

^b University of Illinois at Chicago   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CLOCKS; COPPER; DIAGNOSTIC RADIOGRAPHY; DIGITAL CIRCUITS; DISTRIBUTED PARAMETER NETWORKS; DISTRIBUTION OF GOODS; ELECTRIC CLOCKS; ELECTRIC IMPEDANCE; ELECTRIC IMPEDANCE TOMOGRAPHY; ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER SYSTEM INTERCONNECTION; INTEGRATED CIRCUITS; JITTER; MEDICAL IMAGING; OPTICAL INTERCONNECTS; SIGNAL PROCESSING; TECHNOLOGY; TIMING JITTER; VLSI CIRCUITS;

ALTERNATIVE APPROACHES; BIT ERRORS; CLOCK DISTRIBUTIONS; CLOCK SKEWS; CONTINUOUS IMPROVEMENTS; COPPER INTERCONNECT; DIGITAL SYSTEMS; EXPLORATORY RESEARCHES; FUTURE TECHNOLOGIES; GHZ FREQUENCIES; HIGH SPEEDS; INTER-CONNECTS; INTERCONNECT TECHNOLOGIES; ON CHIPS; OPERATING FREQUENCIES; PERFORMANCE LIMITERS; POWER CONSUMPTIONS; SIGNAL INTEGRITIES;

NETWORKS (CIRCUITS);

EID: 47649104695     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EIT.2007.4374479     Document Type: Conference Paper

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