Inductance enhancement in global clock distribution networks

Proceedings of the IEEE 2004 International Interconnect Technology Conference

Volumn , Issue , 2004, Pages 119-121

  Luman, Heather ^a   Davis, Jeff ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATTENUATION; BANDWIDTH; CMOS INTEGRATED CIRCUITS; CONSTRAINT THEORY; ELECTRIC IMPEDANCE; ELECTRIC INDUCTORS; INDUCTANCE; LEAKAGE CURRENTS; NETWORKS (CIRCUITS);

BANDWIDTH LIMITATIONS; CUT-OFF FREQUENCY; PHASE VELOCITY; SIGNAL TRANSMISSION;

ELECTRIC POWER DISTRIBUTION;

EID: 8644250677     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Outnik, V; Chandrakasan, A. "Active GHz clock network using distributed PLLs". Digest of Technical Papers. 2000 IEEE International Solid State Circuits Conference, 7-9 Feb. 2000.
2. Mule, A.V.; Glytsis, E.N.; Gaylord, T.K.; Meindl, J.D. "Electrical and optical clock distribution networks for gigascale microprocessors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 10 Issue 5, Oct. 2002.
3. Stetson, Sean. "Low jitter clock distribution networks." Dissertation Proposal, University of Michigan. July 17, 1997.
4. Magnusson, Philip C. Transmission Line and Wave Propagation. Boston: Allyn and Bacon, Inc. 1965, p 38-41; 149-150
5. Davis, J.A., Meindl, J.D. "Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions." IEEE Transactions on Electron Devices, Vol. 47, Issue 11. Nov2000. pp. 2068-2077.
6. Pupin, M.I. "A note on loaded conductors" Electrical World and Engineer, Oct. 12, 1901.
7. Level 49 SPICE parameters obtained from www.mosis.org
8. FastCap and FastHenry are available for free download at www.fastfieldsolvers.com