-
1
-
-
0037387774
-
Jitter transfer characteristics of delay-locked loops - theories and design techniques
-
April
-
M.-J.E. Lee et al., "Jitter transfer characteristics of delay-locked loops - theories and design techniques," IEEE J. Solid-State Circuits, vol. 38, pp. 614-621, April 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 614-621
-
-
Lee, M.-J.E.1
-
2
-
-
0035333219
-
A dual-loop delay-locked loop using multiple voltage-controlled delay lines
-
May
-
Y. J. Jung, S. W. Lee, D. Shim, W. Kim and S. I. Cho, "A dual-loop delay-locked loop using multiple voltage-controlled delay lines," IEEE J. Solid-State Circuits, vol.36, no.5, pp. 784-791, May. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.5
, pp. 784-791
-
-
Jung, Y.J.1
Lee, S.W.2
Shim, D.3
Kim, W.4
Cho, S.I.5
-
3
-
-
0036858568
-
A low-power small-area +/7.28-ps-jitter 1-GHz DLL-based clock generator
-
Nov
-
C. Kim, I. C. Hwang, and S. M. Kang, "A low-power small-area +/7.28-ps-jitter 1-GHz DLL-based clock generator," IEEE J. Solid-State Circuits, vol. 37, pp.1414 - 1420, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 1414-1420
-
-
Kim, C.1
Hwang, I.C.2
Kang, S.M.3
-
4
-
-
0033894074
-
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance
-
March
-
Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, "An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance," IEEE J. Solid-State Circuits, vol. 35, pp.377 - 384, March 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 377-384
-
-
Moon, Y.1
Choi, J.2
Lee, K.3
Jeong, D.K.4
Kim, M.K.5
-
5
-
-
0035273837
-
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator
-
March
-
D.J. Foley and M. P. Flynn, "CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator," IEEE J. Solid-State Circuits, Vol. 36, pp.417-423, March 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 417-423
-
-
Foley, D.J.1
Flynn, M.P.2
-
6
-
-
34250780929
-
A delay-locked frequency synthesizer with low phase noise performance
-
Dec
-
Q. Du, J. Zhuang, T. Kwasniewski, "A delay-locked frequency synthesizer with low phase noise performance," IEEE Conference on Electron Devices and Solid-State Circuits, pp.461 - 464, Dec 2003.
-
(2003)
IEEE Conference on Electron Devices and Solid-State Circuits
, pp. 461-464
-
-
Du, Q.1
Zhuang, J.2
Kwasniewski, T.3
-
7
-
-
0036309503
-
RF local oscillator path for GSM direct conversion transceiver with true 50% duty cycle divide by three and active third harmonic cancellation
-
June
-
R. Magoon and A. Molnar, "RF local oscillator path for GSM direct conversion transceiver with true 50% duty cycle divide by three and active third harmonic cancellation," IEEE Radio Frequency Integrated Circuits Symposium, pp. 23-26, June 2002.
-
(2002)
IEEE Radio Frequency Integrated Circuits Symposium
, pp. 23-26
-
-
Magoon, R.1
Molnar, A.2
-
8
-
-
0034484420
-
A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications
-
Dec
-
G. Chien, P. R. Gray, "A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications," IEEE J. Solid-State Circuits, vol. 35, pp. 1996 - 1999, Dec. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 1996-1999
-
-
Chien, G.1
Gray, P.R.2
-
9
-
-
0036684711
-
A wide-range delay-locked loop with a fixed latency of one clock cycle
-
Aug
-
H. H. Chang, J. W. Lin, and C. Y. Yang, "A wide-range delay-locked loop with a fixed latency of one clock cycle," IEEE J. Solid-State Circuits, vol.37, no.8, pp. 1021-1027, Aug. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.8
, pp. 1021-1027
-
-
Chang, H.H.1
Lin, J.W.2
Yang, C.Y.3
-
10
-
-
34250723640
-
A fast-lock DLL with power-on reset circuit
-
May
-
K.H. Chen, Y.L. Lo, "A fast-lock DLL with power-on reset circuit," IEEE ISCAS, pp. 357-360, May. 2004.
-
(2004)
IEEE ISCAS
, pp. 357-360
-
-
Chen, K.H.1
Lo, Y.L.2
|