RF local oscillator path for GSM direct conversion transceiver with true 50% duty cycle divide by three and active third harmonic cancellation

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2002, Pages 23-26

  Magoon, Rahul ^a   Molnar, Alyosha ^a  

^a Rockwell Semiconductor Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; EMITTER COUPLED LOGIC CIRCUITS; FLIP FLOP CIRCUITS; FREQUENCY DOUBLERS; TRANSCEIVERS; UHF DEVICES; VARIABLE FREQUENCY OSCILLATORS;

POLYPHASE FILTERS;

GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS;

EID: 0036309503     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Digital cellular telecommunications system (Phase 2+): Radio transmission and reception
2. Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS
3. A precise four-quadrant multiplier with subnanosecond response
4. A 6-GHz integrated phase-locked loop using AlGaAs/GaAs heterojunction bipolar transistors
5. Design considerations for very-high-speed si-bipolar IC's operating up to 50 Gb/s
6. Design techniques for low-voltage high-speed digital bipolar circuits
7. A single chip quad band (850/900/1800/1900MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-N synthesizer