A delay-locked frequency synthesizer with low phase noise performance

2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Volumn , Issue , 2003, Pages 461-464

  Du, Qingjin ^a   Zhuang, Jingcheng ^a   Kwasniewski, Tad ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON DEVICES; FREQUENCY SYNTHESIZERS; LOCKS (FASTENERS); SOLID STATE DEVICES;

CARRIER FREQUENCY; CMOS TECHNOLOGY; LOW PHASE NOISE; PERIOD JITTER; PHASE NOISE PERFORMANCE; REFERENCE SIGNALS; RF GENERATORS; SYMMETRICAL STRUCTURE;

PHASE NOISE;

EID: 34250780929     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2003.1283573     Document Type: Conference Paper

References (3)

1. David. J.Foley, "CMOS DLL-Based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator", IEEE Journal of Solid-State Circuits, 2001
2. Gray. Chien, P. R. Gray, "A 900-MHz local oscillator using a DLL-based frequency multiplier techniques for PCS applications", IEEE Journal of Solid-State Circuits, 2000
3. Sheng. Ye, L. Jansson, L. Galton, "A multiple-crystal interface PLL with VCO realignment to reduce phase noise", IEEE Solid-State Circuit Conference, Feb, 2002.