Analysis and modeling of threshold voltage mismatch for CMOS at 65 nm and beyond

IEEE Electron Device Letters

Volumn 29, Issue 7, 2008, Pages 802-804

  Johnson, Jeffrey B ^a   Hook, Terence B ^a   Lee, Yoo Mi ^b  

^a IBM MICROELECTRONICS   (United States)

^b IBM RESEARCH   (United States)

Author keywords

CMOSFETs; Doping; Transistors

Indexed keywords

COMPACT MODELING; HALO IMPLANTS; RANDOM DOPANT FLUCTUATION (RDF); TRANSISTOR MISMATCH; VOLTAGE MISMATCH;

THRESHOLD VOLTAGE;

EID: 47249137864     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2000649     Document Type: Article

References (9)

1. D. J. Frank et al., "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
2. V. De et al., " Random MOSFET parameter fluctuation limits to gigascale integration (GSI)," in VLSI Symp. Tech. Dig., 1996, pp. 198-199.
3. R. W. Keyes, "The, effect of randomness in the distribution of impurity atoms on FET thresholds," Appl. Phys., Vol. 8, no. 3, pp. 251-259 Nov. 1975.
4. M. J. M. Polgrom et al., "Matching properties of MOS transistors," IEEE J. Solid State Circuits, Vol. 24, no. 5, pp. 1433-1440, Oct. 1989.
5. R A. Stolk et al., "Modeling statistical dopant fluctuations in MOS transistors," IEEE Trans. Electron Devices, Vol. 45, no. 9, pp. 1960-1971, Sep. 1998.
6. G. Roy et al., "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETS," IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3063-3070, Dec. 2006.
7. B. Cheng et al., "The impact of random doping effects on CMOS SRAM cell," in Proc. ESSCIRC, 2004, pp. 219-222.
8. P. G. Drennan et al., "A comprehensive MOSFET mismatch model," in IEDM Tech. Dig., 1999, pp. 167-170.
9. Z. Luo et al., "High performance and low power transistors integrated in 65 nm bulk CMOS technology," IEDM Tech. Dig., 2004, pp. 661-664.