Variation tolerant high resolution and low latency time-to-digital converter

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 194-197

  Henzler, S ^a   Koeppe, S ^a   Lorenz, D ^a,b   Kamp, W ^a   Kuenemund, R ^a   Schmitt Landsiedel, D ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK UNCERTAINTY; DEAD TIME (DT); DELAY LINE (DL); EUROPEAN; HIGH RESOLUTIONS; INVERTER DELAYS; LOCAL VARIATIONS; LOW LATENCY; LOW POWER CMOS; PASSIVE VOLTAGE; PROCESS VARIATIONS; RESOLUTION LIMITS; SOLID-STATE CIRCUITS CONFERENCE; TIME QUANTIZATION; TIME-TO-DIGITAL CONVERTER (TDC);

ANALOG TO DIGITAL CONVERSION; COMPUTER NETWORKS; DIGITAL ARITHMETIC; FREQUENCY CONVERTERS; TECHNOLOGY;

VOLTAGE DIVIDERS;

EID: 44849100549     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430278     Document Type: Conference Paper

References (9)

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