FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic

IEEE Transactions on Signal Processing

Volumn 56, Issue 7 I, 2008, Pages 3009-3017

  Meher, Pramod Kumar ^a   Chandrasekaran, Shrutisagar ^b   Amira, Abbes ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b BRUNEL UNIVERSITY   (United Kingdom)

Author keywords

Distributed arithmetic; Field programmable gate arrays (FPGA); Finite impulse response (FIR) filter; Linear convolution; Systolic array

Indexed keywords

BRAIN; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FILTER BANKS; OPTIMIZATION; SHAPE OPTIMIZATION; STRUCTURAL OPTIMIZATION; TWO DIMENSIONAL; WAVE FILTERS;

(ALGORITHMIC) COMPLEXITY; ADDER COMPLEXITY; COMPUTING UNITS; DECOMPOSITION SCHEME; DESIGN OPTIMIZATION (DO); DISTRIBUTED ARITHMETIC (DA); DYNAMIC POWER CONSUMPTION; ENERGY DENSITIES; ENERGY THROUGHPUT; FPGA IMPLEMENTATIONS; HANDEL-C; IN LINE; LOOK-UP TABLES (LUT); MAXIMUM USABLE FREQUENCY; MEMORY SIZE; PERFORMANCE METRICS; POWER EFFICIENT; TWO-DIMENSIONAL (2D); XILINX VIRTEX;

FIR FILTERS;

EID: 46749136512     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSP.2007.914926     Document Type: Article

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