Cost-effective novel flexible cell-level systolic architecture for high throughput implementation of 2-D FIR filters

IEE Proceedings: Computers and Digital Techniques

Volumn 143, Issue 6, 1996, Pages 436-439

  Mohanty, B K ^a   Meher, P K ^b  

^a S K C G College   (India)

^b BERHAMPUR UNIVERSITY   (India)

Author keywords

2 D FIR filters; 2 D linear phase FIR filters; Systolic architecture; VLSI

Indexed keywords

DATA STRUCTURES; DIGITAL FILTERS; MATHEMATICAL TECHNIQUES; PROGRAM PROCESSORS; SYSTOLIC ARRAYS; VLSI CIRCUITS;

LINEAR PHASE RESPONSE; SYSTOLIC ARCHITECTURE;

PARALLEL PROCESSING SYSTEMS;

EID: 0030286422     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19960423     Document Type: Article

References (8)

1. LAMPROPOULOS, G.A., and FAHMY, M.M.: 'A new realisation for 2-D digital filters', IEEE Trans., 1987, ASSP-35, pp. 533-542
2. SID-AHMED, M.A.: 'A systolic realisation for 2-D digital filters', IEEE Trans., 1989, ASSP-37, pp. 560-565
3. SUNDER, S., EL-GUIBALY, F., and ANTONIOU, A.: 'Systolic implementation of two-dimensional recursive digital filters', IEEE Proc., Int. Symp. Circuits Syst., 1990, pp. 1034-1037
4. SUNDER, S., EL-GUIBALY, F., and ANTONIOU, A.: 'Systolic implementation of digital filters', Multidimensional Systems and Signal Processing, 3, pp. 63-78
5. SHANBHAG, N.R.: 'An improved systolic architecture for 2-D digital filters', IEEE Trans., 1991, SP-39, pp. 1195-1202
6. KWAN, H.K., and TSIM, M.T.: 'Efficient systolic high-speed architectures for delayed multipath two-dimensional FIR and IIR digital filtering', IEE Proc. G, 1990, 137, pp. 413-423
7. POWELL, S.R., and CHAU, P.M.: 'A technique for realising linear phase IIR filters', IEEE Trans., 1991, SP-39, pp. 2425-2435
8. McCALLA, T.R.: 'Introduction to numerical methods and FORTRAN programming' (John Wiley and Sons, Inc., USA, 1967)