FPGA implementation of FIR filter using M-bit parallel distributed arithmetic

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 875-878

  Jeng, Shiann Shiun ^a   Lin, Hsing Chen ^a   Chang, Shu Ming ^b  

^a NATIONAL DONG HWA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MULTIPLYING CIRCUITS; PARALLEL ALGORITHMS;

FPGA IMPLEMENTATION; PARALLEL DISTRIBUTED ARITHMETIC;

FIR FILTERS;

EID: 34547272702     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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