Hardware-efficient distributed arithmetic architecture for high-order digital filters

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn V, Issue , 2005, Pages

  Yoo, Heejong ^a   Anderson, David V ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS; FIR FILTERS; TABLE LOOKUP; TRANSISTORS;

BINARY CODING; DISTRIBUTED ARITHMETIC (DA) ARCHITECTURE; LOGIC ELEMENT (LE); LUT-BASED DA;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 33646781953     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2005.1416256     Document Type: Conference Paper

References (7)

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