Automatic FIR filter generation for FPGAs

Lecture Notes in Computer Science

Volumn 3553, Issue , 2005, Pages 51-61

  Ruckdeschel, Holger ^a   Dutta, Hritam ^a   Hannig, Frank ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; FIELD PROGRAMMABLE GATE ARRAYS; HIERARCHICAL SYSTEMS; OPTIMIZATION; SPEED CONTROL; VLSI CIRCUITS;

DESIGN FLOW; PARALLEL VLSI ARCHITECTURES; PARO DESIGN; PARTIAL LOCALIZATION;

FIR FILTERS;

EID: 26444524332     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11512622_7     Document Type: Conference Paper

References (17)

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