Voltage island generation under performance requirement for SoC designs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 798-803

  Mak, Wai Kei ^a   Chen, Jr Wei ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER TRANSMISSION NETWORKS; ENERGY CONSERVATION; INDUSTRIAL ENGINEERING; LANDFORMS; LEAD; MECHANIZATION; PROGRAMMABLE LOGIC CONTROLLERS;

ASSIGNMENT PROBLEM (AP); CHIP AREAS; COMPLEX POWER; DESIGN AUTOMATION CONFERENCE (DAC); FLOOR-PLANNING; LEVEL SHIFTERS; LOW POWERS; MULTIPLE SUPPLY VOLTAGES; OPTIMALITY; PERFORMANCE REQUIREMENTS; POWER NETWORKS; POWER SAVINGS; SOC DESIGNS; SOUTH PACIFIC; SYSTEM-ON-A-CHIP (SOC) DESIGNS; TOTAL POWER CONSUMPTION; VOLTAGE ISLANDS; VOLTAGE LEVELS; WIRE LENGTHS;

POWER GENERATION;

EID: 46649113752     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358087     Document Type: Conference Paper

References (13)

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