Minimizing power with flexible voltage Islands

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 21-24

  Puri, Ruchir ^a   Kung, David ^a   Stok, Leon ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL REGION; DESIGN CONSTRAINTS; DESIGN IMPLEMENTATION; HIGH PERFORMANCE APPLICATIONS; LEVEL SHIFTER; MULTIPLE SUPPLY VOLTAGES; MULTIPLE THRESHOLD; MULTIPLE VOLTAGE; NANOMETER TECHNOLOGY; PHYSICAL LAYOUT; POWER DISSIPATION; POWER EFFICIENCY; STANDARD CELL; TIMING CONSTRAINTS; VOLTAGE ISLAND;

ELECTRIC BATTERIES; TIMING CIRCUITS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 33845434899     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464514     Document Type: Conference Paper

References (21)

1. R. Brodersen et al., Methods for true power minimization, ICCAD 2002.
2. K. Usami and M. Horowitz, Clustered voltage scaling techniques for low-power Design, ISLPED 1995.
3. M. Hamada, Y. Ootaguro, and T. Kuroda, Utilizing surplus timing for power reduction, CICC 2001, p.89-92.
4. K. Usami, et al., Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor, IEEE JSSC, Vol.33, No.3, 1998.
5. C. Chen, A. Srivastava, and M. Sarrafzadeh, On gate level power optimization using dual-supply voltages, IEEE Trans, on VLSI Systems, vol.9, p.616-629, Oct. 2001.
6. N. Rohrer, et al., A 480MHz RISC microprocessor in a 0.12μn Leff CMOS technology with copper interconnects, ISSCC 1998, p.240-241.
7. S. Sirichotiyakul, et al., Standby power minimization through simultaneous threshold voltage selection and circuit sizing, DAC 1999, p.436-441.
8. Q. Wang and S.Vrudhula, Algorithms for minimizing standby power in deep submicron, dual-Vt CMOS circuits, IEEE Transactions on CAD, vol.21, p.306-318, 2002.
9. R. Puri, Minimizing power under performance constraint, IEEE Intl. Conf. on IC Design and Technology, 2004.
10. R. Puri et al., Pushing Power in a Performance Envelope, DAC 2003.
11. M. Hamada, et al., A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme, CICC 1998, p.495-498.
12. D. Sylvester and H. Kaul, Future performance challenges in nanometer design, DAC 2001, p.3-8.
13. A. Srivastava and D. Sylvester, Minimizing total power by simultaneous Vdd/Vth assignment, Proc. Asia-South Pacific DAC 2003, p.400-403.
14. C. Yeh, et al., Layout Techniques supporting the use of Dual Supply Voltages for Cell-based Designs, DAC 1999.
15. D. Lackey, et al., Managing Power and Performance for SOC Designs using voltage islands, ICCAD 2002.
16. S. Kosonocky, et al., Low Power Circuits and Technology for wireless digital Systems, IBM Journal of R&D, Vol. 47, No. 2/3, 2003.
17. A. Correale, D. Pan, D. Lamb, D. Wallach, D. Kung, R. Puri, Generic Voltage Island: CAD Flow and Design Experience, Austin Conference on Energy Efficient Design, March 2003 (IBM Research Report)
18. L. Trevillyan, D. Kung, R. Puri, L. Reddy, M. Kazda, An Integrated Environment for Design Closure of Deep-submicron ICs, IEEE Design and Test, February 2004.
19. R. Puri, E. D'souza, L. Reddy, W. Scarpero, B. Wilson, Optimizing Power-Performance with Multi-Threshold Cull -CuO8 ASIC Libraries, Austin Conference on Energy Efficient Design, March 2003 (IBM Research Report).
20. R. Puri, D. Pan, D. Kung, A Flexible Design Approach for the Use of Dual Supply Voltages and Level Conversion for Low-Power ASIC Design, Austin Conference on Energy Efficient Design, March 2003 (IBM Research Report).
21. Y. Taur, CMOS Design near the limit of scaling, IBM Journal of R&D, Vol. 46, No. 2/3, 2002.