Timing-driven soft-macro resynthesis method in interaction with chip floorplanning

Proceedings - Design Automation Conference

Volumn , Issue , 1999, Pages 262-267

  Su, Hsiao Pin ^a   Wu, Allen C H ^a   Lin, Youn Long ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT;

CHIP FLOORPLANNING; TIMING-DRIVEN SOFT-MACRO RESYNTHESIS METHODS;

MICROPROCESSOR CHIPS;

EID: 0032638530     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (17)