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Volumn , Issue , 2007, Pages 268-273

A theoretical study on wire length estimation algorithms for placement with opaque blocks

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK PLACEMENT; DESIGN AUTOMATION CONFERENCE (DAC); RESEARCH RESULTS; ROUTING LENGTH; SOUTH PACIFIC; VLSI CAD; WIRE LENGTH ESTIMATION;

EID: 46649108948     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.357997     Document Type: Conference Paper
Times cited : (4)

References (10)
  • 1
    • 0003651533 scopus 로고
    • Parallel rectilinear shortest paths with rectangular obstacles
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    • (1991) Computational Geometry: Theory and Applications , vol.1 , Issue.2 , pp. 79-113
    • Atallah, M.J.1    Chen, D.Z.2
  • 2
    • 29144505066 scopus 로고    scopus 로고
    • Are floorplan representations important in digital design?
    • H. H. Chan, S. N. Adya, and I. L. Markov, "Are floorplan representations important in digital design?" ISPD'05, pp. 129-136, 2005.
    • (2005) ISPD'05 , pp. 129-136
    • Chan, H.H.1    Adya, S.N.2    Markov, I.L.3
  • 3
    • 0033701594 scopus 로고    scopus 로고
    • B*-trees: A new representation for non-slicing floorplans
    • Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S-W. Wu, "B*-trees: a new representation for non-slicing floorplans," DAC'00, pp. 458-463, 2000.
    • (2000) DAC'00 , pp. 458-463
    • Chang, Y.-C.1    Chang, Y.-W.2    Wu, G.-M.3    Wu, S.-W.4
  • 4
    • 33745939461 scopus 로고    scopus 로고
    • Toward better wireload models in the presence of obstacles
    • C.-K. Cheng, A. B. Kahng, B. Liu, and D. Stroobandt, "Toward better wireload models in the presence of obstacles," ASPDAC'01, pp. 527-532, 2001.
    • (2001) ASPDAC'01 , pp. 527-532
    • Cheng, C.-K.1    Kahng, A.B.2    Liu, B.3    Stroobandt, D.4
  • 5
    • 13444250462 scopus 로고    scopus 로고
    • A novel encoding method into sequence-pair
    • C. Kodama, K. Fujiyoshi, and T. Koga, "A novel encoding method into sequence-pair," ISCAS'04, pp. 329-332, 2004.
    • (2004) ISCAS'04 , pp. 329-332
    • Kodama, C.1    Fujiyoshi, K.2    Koga, T.3
  • 6
    • 46649096031 scopus 로고    scopus 로고
    • J. S.B. Mitchell, Geometric shortest paths and network optimization, Handbook of Computational Geometry, Elsevier Science, pp. 633-702, 2000.
    • J. S.B. Mitchell, "Geometric shortest paths and network optimization," Handbook of Computational Geometry, Elsevier Science, pp. 633-702, 2000.
  • 7
    • 0030378255 scopus 로고    scopus 로고
    • VLSI module placement based on rectangle-packing by the sequence pair
    • H. Murata, K. Fujiyoshi, S. Nakatake, and Y Kajitani, "VLSI module placement based on rectangle-packing by the sequence pair," IEEE TCAD, Vol.15, No. 12, pp. 1518-1524, 1996.
    • (1996) IEEE TCAD , vol.15 , Issue.12 , pp. 1518-1524
    • Murata, H.1    Fujiyoshi, K.2    Nakatake, S.3    Kajitani, Y.4
  • 8
    • 84941482028 scopus 로고
    • Rectilinear shortest paths with rectangular barriers
    • P. J. de Rezende, D. T. Lee and Y. F. Wu, "Rectilinear shortest paths with rectangular barriers," SCG'85, pp. 204-213, 1985.
    • (1985) SCG'85 , pp. 204-213
    • de Rezende, P.J.1    Lee, D.T.2    Wu, Y.F.3
  • 10
    • 2442582530 scopus 로고    scopus 로고
    • Space-planning: Placement of modules with controlled empty area by single-sequence
    • X. Zhang and Y Kajitani. "Space-planning: Placement of modules with controlled empty area by single-sequence," ASPDAC'04, pp. 25-30, 2004.
    • (2004) ASPDAC'04 , pp. 25-30
    • Zhang, X.1    Kajitani, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.