Toward better wireload models in the presence of obstacles

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 527-532

  Cheng, Chung Kuan ^a   Kahng, A B ^a   Liu, Bao ^a   Stroobandt, D ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b GHENT UNIVERSITY   (Belgium)

Author keywords

Convergence; Delay estimation; Electronic design automation and methodology; Parameter estimation; Path planning; Routing; System on a chip; Table lookup; Wire; Yield estimation

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATION; COMPUTER AIDED DESIGN; DESIGN; INTEGRATED CIRCUIT DESIGN; MICROPROCESSOR CHIPS; MOTION PLANNING; PARAMETER ESTIMATION; SYSTEM-ON-CHIP; TABLE LOOKUP; WIRE;

CONVERGENCE; DELAY ESTIMATION; ELECTRONIC DESIGN AUTOMATION AND METHODOLOGIES; ROUTING; SYSTEM ON A CHIP; YIELD ESTIMATION;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 33745939461     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913362     Document Type: Conference Paper

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