Optimum prefix adders in a comprehensive area, timing and power design space

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 609-615

  Liu, Jianhua ^a   Zhu, Yi ^a   Zhu, Haikun ^a   Cheng, Chung Kuan ^a   Lillis, John ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b 1120 Science and Engineering Offices   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRIVAL TIME; ASIC DESIGNS; BUFFER INSERTION; DESIGN AUTOMATION CONFERENCE (DAC); GATE SIZING; HIGH LEVEL SYNTHESIS (HLS); INTEGER LINEAR PROGRAMMING (ILP); PARALLEL PREFIX ADDERS; POWER DESIGNS; POWER MODELING; PREFIX ADDERS; REQUIRED TIME; SOUTH PACIFIC; STATIC AND DYNAMIC;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; DYNAMIC MODELS; GATES (TRANSISTOR); INDUSTRIAL ENGINEERING; INTEGER PROGRAMMING; INTEGRATED CIRCUITS; LINEAR PROGRAMMING; LINEARIZATION; MECHANIZATION; TERMINOLOGY; TIME MEASUREMENT;

ADDERS;

EID: 46649101846     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358053     Document Type: Conference Paper

References (13)

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