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Volumn 4863, Issue , 2002, Pages 109-120

Power-speed trade-off in parallel prefix circuits

Author keywords

Parallel prefix circuits; Power; Power speed trade off

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; PARALLEL PROCESSING SYSTEMS; THROUGHPUT;

EID: 0036417569     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.472935     Document Type: Conference Paper
Times cited : (2)

References (14)
  • 6
    • 84976772007 scopus 로고
    • Parallel prefix computation
    • R.E. Ladner, and M.J. Fischer, "Parallel Prefix Computation", Journal of ACM, Vol. 27, pp. 831-838, 1980.
    • (1980) Journal of ACM , vol.27 , pp. 831-838
    • Ladner, R.E.1    Fischer, M.J.2
  • 9
    • 0032593423 scopus 로고    scopus 로고
    • A new class of depth-size optimal parallel prefix circuits
    • Y.M. Lin, and C.C. Shih, "A New Class of Depth-Size Optimal Parallel Prefix Circuits", Journal of Supercomputing, Vol. 14, pp. 39-52, 1999.
    • (1999) Journal of Supercomputing , vol.14 , pp. 39-52
    • Lin, Y.M.1    Shih, C.C.2
  • 10
    • 0011352720 scopus 로고    scopus 로고
    • Chapter 6: Designing combinational logic gates in CMOS
    • early draft of the 2nd edition, April
    • J.M. Rabaey, A. Chandrakasan, and B. Nikolic, "Chapter 6: Designing Combinational Logic Gates in CMOS", Digital Integrated Circuits A Design Perspective, early draft of the 2nd edition, April 2001, http://bwrc.eecs.berkeley.edu/Classes/IcBook/2ndEdition.html.
    • (2001) Digital Integrated Circuits A Design Perspective
    • Rabaey, J.M.1    Chandrakasan, A.2    Nikolic, B.3
  • 12
    • 38249038609 scopus 로고
    • Depth-size tradeoffs for parallel prefix computation
    • M. Snir, "Depth-Size Tradeoffs for Parallel Prefix Computation", Journal of Algorithms, Vol. 17, pp. 185-201, 1986.
    • (1986) Journal of Algorithms , vol.17 , pp. 185-201
    • Snir, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.