Constructing zero-deficiency parallel prefix adder of minimum depth

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 883-888

  Zhu, Haikun ^a   Cheng, Chung Kuan ^a   Graham, Ronald ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

BINARY ADDITIONS; BIT-WIDTH; DELAY MODELING; LOGICAL EFFORT; PARALLEL PREFIX ADDER; PREFIX ADDERS; VLSI DESIGN;

ADDERS;

EID: 43249130854     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1121061     Document Type: Conference Paper

References (18)

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