Processor power reduction via single-isa heterogeneous multi-core architectures

IEEE Computer Architecture Letters

Volumn 2, Issue 1, 2003, Pages 2-

  Kumar, Rakesh ^a   Farkas, Keith ^b   Jouppi, Norman P ^b   Ranganathan, Partha ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85008065233     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2003.6     Document Type: Article

References (11)

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