On the automatic transactor generation for TLM-based design flows

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2006, Pages 85-92

  Bombieri, Nicola ^a   Fummi, Franco ^a  

^a UNIVERSITY OF VERONA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

(ALGORITHMIC) COMPLEXITY; ABSTRACTION LEVELS; COMMUNICATION ENVIRONMENTS; DESIGN FLOWS; DIGITAL SYSTEMS DESIGN; EXTENDED FINITE STATE MACHINE (EFSM) MODEL; GENERATION PROCESS; HIGH LEVEL DESIGNS; INTERNATIONAL (CO); TEST BENCHES; TRANSACTION-LEVEL MODELING (TLM);

ABSTRACTING; FLOW SIMULATION; STANDARDS;

TESTING;

EID: 46249124770     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2006.319969     Document Type: Conference Paper

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