Modeling a reconfigurable system for computing the FFT in place via rewriting-logic

Proceedings - 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003

Volumn , Issue , 2003, Pages 205-210

  Ayala Rincon M ^a   Nogueira, R B ^a   Llanos, C H ^a   Jacobi, R P ^a   Hartenstein, R W ^b  

^a UNIVERSITY OF BRASILIA   (Brazil)

^b Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

Application specific integrated circuits; Brazil Council; Circuit simulation; Computational modeling; Computer architecture; Costs; Field programmable gate arrays; Hardware; Reconfigurable architectures; Signal processing algorithms

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CIRCUIT SIMULATION; COMPUTATION THEORY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COSTS; DESIGN; FAST FOURIER TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUITS; RECONFIGURABLE HARDWARE; SIGNAL PROCESSING; SIGNAL RECEIVERS; STRUCTURAL DESIGN; SYSTEMS ANALYSIS;

BRAZIL COUNCIL; COMPUTATIONAL MODEL; DYNAMICALLY RECONFIGURABLE ARCHITECTURE; EFFICIENT ARCHITECTURE; MODEL AND SIMULATION; RECONFIGURABLE SYSTEMS; RECONFIGURATION SCHEMES; SIGNAL PROCESSING ALGORITHMS;

RECONFIGURABLE ARCHITECTURES;

EID: 84945382151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2003.1232830     Document Type: Conference Paper

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