Energy conscious simultaneous voltage scaling and on-chip communication bus synthesis

IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip

Volumn , Issue , 2006, Pages 296-301

  Pandey, Sujan ^a   Murgan, Tudor ^a   Glesner, Manfred ^a  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BREEDER REACTORS; BUSBARS; BUSES; COMMUNICATION; COMMUNICATION CHANNELS (INFORMATION THEORY); CONSERVATION; ENERGY EFFICIENCY; ENERGY POLICY; INTEGRATED CIRCUITS; LSI CIRCUITS; MATHEMATICAL PROGRAMMING; MICROPROCESSOR CHIPS; NONLINEAR PROGRAMMING; PROGRAMMABLE LOGIC CONTROLLERS; TECHNOLOGY;

BODY BIASING; BUS WIDTH; CHALLENGING TASK; COMPUTATIONAL COSTS; DESIGN SPACES; ENERGY EFFICIENT; ENERGY EFFICIENT COMMUNICATIONS; ENTIRE SYSTEM; EXPERIMENTAL RESULTS; INTERNATIONAL CONFERENCES; ON CHIP BUSES; ON CHIP COMMUNICATIONS; OPTIMAL SIZE; RESOURCE SELECTION; SIMULATION BASED TECHNIQUES; SYNTHESIS (OF CHIRAL IONIC LIQUIDS); SYSTEM COMPLEXITY; SYSTEM DESIGNERS; SYSTEM ON CHIP (SOCS); TECHNOLOGY SCALING; TOTAL ENERGIES; TOTAL ENERGY CONSUMPTION; VERY LARGE SCALE INTEGRATION (VLSI); VOLTAGE-SCALING;

ENERGY CONSERVATION;

EID: 46249106501     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2006.313250     Document Type: Conference Paper

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