Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture

SBCCI 2005 - 18th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2005, Pages 230-235

  Pandey, Sujan ^a   Glesner, Manfred ^a   Mühlhäuser, Max ^a  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Algorithms; On chip communication architecture synthesis; Optimization

Indexed keywords

BREEDER REACTORS; BUSES; COMPLEXATION; INTEGER PROGRAMMING; INTEGRATED CIRCUITS; LINEAR PROGRAMMING; LINEARIZATION; OPTIMIZATION; SYSTEMS ANALYSIS; TOPOLOGY; UBIQUITOUS COMPUTING;

BUS WIDTH; COMMUNICATION ARCHITECTURES; COMMUNICATION BEHAVIORS; COMMUNICATION TOPOLOGIES; COMPLEX SYSTEMS; INTEGER LINEAR PROGRAMMING (ILP); ON CHIP COMMUNICATIONS; ON CHIPS; SYNTHESIS (OF CHIRAL IONIC LIQUIDS); SYSTEM LEVEL PROFILING; SYSTEMS DESIGN;

COMMUNICATION;

EID: 34648834455     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2005.4286862     Document Type: Conference Paper

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