메뉴 건너뛰기




Volumn , Issue , 2006, Pages 7-12

A fast block structure preserving model order reduction for inverse inductance circuits

Author keywords

Inductance and interconnect modeling; Model order reduction

Indexed keywords

BLOCK STRUCTURED; COMPUTER-AIDED DESIGN; INTERNATIONAL CONFERENCES; INVERSE INDUCTANCE;

EID: 46149109491     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320098     Document Type: Conference Paper
Times cited : (13)

References (13)
  • 1
    • 0032139262 scopus 로고    scopus 로고
    • PRIMA: Passive reduced-order interconnect macro-modeling algorithm
    • A. Odabasioglu, M. Celik, and L. Pileggi, "PRIMA: Passive reduced-order interconnect macro-modeling algorithm," IEEE Trans. on CAD, pp. 645-654, 1998.
    • (1998) IEEE Trans. on CAD , pp. 645-654
    • Odabasioglu, A.1    Celik, M.2    Pileggi, L.3
  • 2
    • 0016035432 scopus 로고
    • Equivalent circuits models for three dimensional multiconductor systems
    • A. E. Ruehli, "Equivalent circuits models for three dimensional multiconductor systems," IEEE Trans. on MTT, pp. 216-220, 1974.
    • (1974) IEEE Trans. on MTT , pp. 216-220
    • Ruehli, A.E.1
  • 3
    • 0034474751 scopus 로고    scopus 로고
    • How to efficiently capture on-chip inductance effects: Introducing a new circuit element K
    • A. Devgan, H. Ji, and W. Dai, "How to efficiently capture on-chip inductance effects: introducing a new circuit element K," in Proc. ICCAD, 2000.
    • (2000) Proc. ICCAD
    • Devgan, A.1    Ji, H.2    Dai, W.3
  • 4
    • 23744433491 scopus 로고    scopus 로고
    • A provably passive and cost efficient model for inductive interconnects
    • H. Yu and L. He, "A provably passive and cost efficient model for inductive interconnects," IEEE Trans. on CAD, pp. 1283-1294, 2005.
    • (2005) IEEE Trans. on CAD , pp. 1283-1294
    • Yu, H.1    He, L.2
  • 5
    • 0016519919 scopus 로고
    • The modified nodal approach to network analysis
    • C. W. Ho, A. E. Ruehli, and P. A. Brennan, "The modified nodal approach to network analysis," IEEE Trans. on CAS, pp. 504-509, 1975.
    • (1975) IEEE Trans. on CAS , pp. 504-509
    • Ho, C.W.1    Ruehli, A.E.2    Brennan, P.A.3
  • 6
    • 0036911591 scopus 로고    scopus 로고
    • Robust and passive model order reduction for circuits containing susceptance elements
    • H. Zheng and L. T. Pileggi, "Robust and passive model order reduction for circuits containing susceptance elements," in Proc. ICCAD, 2002.
    • (2002) Proc. ICCAD
    • Zheng, H.1    Pileggi, L.T.2
  • 7
    • 0032676524 scopus 로고    scopus 로고
    • ENOR: Model order reduction of RLC circuits using nodal equations for efficient factorization
    • B. N. Sheehan, "ENOR: Model order reduction of RLC circuits using nodal equations for efficient factorization," in Proc. DAG, 1999.
    • (1999) Proc. DAG
    • Sheehan, B.N.1
  • 8
    • 16244386523 scopus 로고    scopus 로고
    • SAPOR: Second-order arnoldi method for passive order reduction of RCS circuits
    • Y. Su, J. Wang, and et. al., "SAPOR: Second-order arnoldi method for passive order reduction of RCS circuits," in Proc. ICCAD, 2004.
    • (2004) Proc. ICCAD
    • Su, Y.1    Wang, J.2    and et., al.3
  • 9
    • 0346148440 scopus 로고    scopus 로고
    • SuPREME: Substrate and power-delivery reluctance-enhanced macromodel evaluation
    • T. Chen, C. Luk, H. Kim, and C. Chen, "SuPREME: Substrate and power-delivery reluctance-enhanced macromodel evaluation," in Proc. ICCAD, 2003.
    • (2003) Proc. ICCAD
    • Chen, T.1    Luk, C.2    Kim, H.3    Chen, C.4
  • 10
    • 16244364781 scopus 로고    scopus 로고
    • SPRIM: Structure-preserving reduced-order interconnect macro-modeling
    • R. W. Freund, "SPRIM: Structure-preserving reduced-order interconnect macro-modeling," in Proc. ICCAD, 2004.
    • (2004) Proc. ICCAD
    • Freund, R.W.1
  • 11
    • 33746809878 scopus 로고    scopus 로고
    • Block structure preserving model reduction
    • H. Yu, L. He, and S.-D. Tan, "Block structure preserving model reduction," in IEEE BMAS-workshop, 2005.
    • (2005) IEEE BMAS-workshop
    • Yu, H.1    He, L.2    Tan, S.-D.3
  • 13
    • 0033099622 scopus 로고    scopus 로고
    • Multilevel hypergraph partitioning: Application in VLSI domain
    • G. Karypis, R. Aggarwal, and V. K. S. Shekhar, "Multilevel hypergraph partitioning: application in VLSI domain," IEEE-Trans. on VLSI, pp. 69-79, 1999.
    • (1999) IEEE-Trans. on VLSI , pp. 69-79
    • Karypis, G.1    Aggarwal, R.2    Shekhar, V.K.S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.