-
1
-
-
46149108100
-
-
International Technology Roadmap for Semiconductors. 〈http://public.itrs.net〉, 2004.
-
International Technology Roadmap for Semiconductors. 〈http://public.itrs.net〉, 2004.
-
-
-
-
2
-
-
0031575290
-
A single electron transistor made from a cadmium selenide nanocrystal
-
Klein D., et al. A single electron transistor made from a cadmium selenide nanocrystal. Nature 389 (1997) 699-701
-
(1997)
Nature
, vol.389
, pp. 699-701
-
-
Klein, D.1
-
3
-
-
0013068352
-
High performance electrolyte-gated carbon nanotube transistors
-
Rosenblatt S., Yaish Y., Park J., Gore J., Sazonova V., and McEuen P.L. High performance electrolyte-gated carbon nanotube transistors. Nano Lett. 2 (2002) 869
-
(2002)
Nano Lett.
, vol.2
, pp. 869
-
-
Rosenblatt, S.1
Yaish, Y.2
Park, J.3
Gore, J.4
Sazonova, V.5
McEuen, P.L.6
-
4
-
-
79956022434
-
Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes
-
Wind S.J., Appenzeller J., Martel R., Derycke V., and Avouris P. Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes. Appl. Phys. Lett. 80 (2002) 3817
-
(2002)
Appl. Phys. Lett.
, vol.80
, pp. 3817
-
-
Wind, S.J.1
Appenzeller, J.2
Martel, R.3
Derycke, V.4
Avouris, P.5
-
5
-
-
3142671577
-
AC performance of nanoelectronics: towards a Ballistic THz nanotube transistor
-
Burke P.J. AC performance of nanoelectronics: towards a Ballistic THz nanotube transistor. Solid-State Electron. 48 (2004) 1981
-
(2004)
Solid-State Electron.
, vol.48
, pp. 1981
-
-
Burke, P.J.1
-
6
-
-
21644460518
-
-
X. Huo, M. Zhang, P.C.H. Chan, Q. Liang, Z.K. Tang, High-frequency S. parameters characterization of back-gate carbon nanotube field-effect transistors, in: IEEE IEDM Tech. Digest, 2004, p. 691.
-
X. Huo, M. Zhang, P.C.H. Chan, Q. Liang, Z.K. Tang, High-frequency S. parameters characterization of back-gate carbon nanotube field-effect transistors, in: IEEE IEDM Tech. Digest, 2004, p. 691.
-
-
-
-
7
-
-
46149127327
-
-
A.O. Orlov, R. Kummamuru, J. Timler, C.S. Lent, G.L. Snider, G.H. Bernstein, Experimental studies of quantum-dot cellular automata devises, Mesoscopic Tunnelling Devices, 2004, ISBN: 81-271-0007-2.
-
A.O. Orlov, R. Kummamuru, J. Timler, C.S. Lent, G.L. Snider, G.H. Bernstein, Experimental studies of quantum-dot cellular automata devises, Mesoscopic Tunnelling Devices, 2004, ISBN: 81-271-0007-2.
-
-
-
-
8
-
-
0031042352
-
Experimental implementation of fast quantum searching
-
Cory D., Fahmy A., and Havel T. Experimental implementation of fast quantum searching. Proc. Natl. Acad. Sci. USA 94 (1997) 1634
-
(1997)
Proc. Natl. Acad. Sci. USA
, vol.94
, pp. 1634
-
-
Cory, D.1
Fahmy, A.2
Havel, T.3
-
9
-
-
0032516155
-
A silicon-based nuclear spin quantum computer
-
Kane B. A silicon-based nuclear spin quantum computer. Nature 393 (1998) 133
-
(1998)
Nature
, vol.393
, pp. 133
-
-
Kane, B.1
-
10
-
-
0036802956
-
Nanostructure array fabrication with temperature-controlled self-assembly techniques
-
Ng V., et al. Nanostructure array fabrication with temperature-controlled self-assembly techniques. Nanotechnology 13 (2002) 554-558
-
(2002)
Nanotechnology
, vol.13
, pp. 554-558
-
-
Ng, V.1
-
11
-
-
0030901567
-
Self-assembly of mesoscale objects into ordered two-dimensional arrays
-
Bowden N., Terfort A., Carbeck J., and Whitesides G.M. Self-assembly of mesoscale objects into ordered two-dimensional arrays. Science 276 (1997) 233-235
-
(1997)
Science
, vol.276
, pp. 233-235
-
-
Bowden, N.1
Terfort, A.2
Carbeck, J.3
Whitesides, G.M.4
-
12
-
-
46149092742
-
-
A. DeHon, et al., Sub-lithographic semiconductor computing systems, Appearing in HotChips 15, Stanford University, August 17-19, 2003.
-
A. DeHon, et al., Sub-lithographic semiconductor computing systems, Appearing in HotChips 15, Stanford University, August 17-19, 2003.
-
-
-
-
13
-
-
0141499770
-
Array-based architecture for FET-based, nanoscale electronics
-
DeHon A. Array-based architecture for FET-based, nanoscale electronics. IEEE Trans. Nanotechnol. 2 1 (2003) 23-32
-
(2003)
IEEE Trans. Nanotechnol.
, vol.2
, Issue.1
, pp. 23-32
-
-
DeHon, A.1
-
14
-
-
33748541157
-
-
S. Goldstein, et al., Reconfigurable computing and electronic nanotechnology, ASAP '03, June 2003, pp. 132-142.
-
S. Goldstein, et al., Reconfigurable computing and electronic nanotechnology, ASAP '03, June 2003, pp. 132-142.
-
-
-
-
15
-
-
0037293712
-
A system architecture solution for unreliable nanoelectronic devices
-
Han J., and Jonen P. A system architecture solution for unreliable nanoelectronic devices. Nanotechnology 14 2 (2003) 224-230
-
(2003)
Nanotechnology
, vol.14
, Issue.2
, pp. 224-230
-
-
Han, J.1
Jonen, P.2
-
16
-
-
0032510985
-
-
J.R. Heath, P.J. Kuekes, G.S. Snider, R.S. Williams, A defect-tolerant architecture: opportunities for nanotechnologies, Science 280 (1998) 1716-1721.
-
J.R. Heath, P.J. Kuekes, G.S. Snider, R.S. Williams, A defect-tolerant architecture: opportunities for nanotechnologies, Science 280 (1998) 1716-1721.
-
-
-
-
18
-
-
0028715170
-
-
D. Gajski, L. Ramacahndran, Introduction to high level synthesis, IEEE Design Test Comput., October 1994.
-
D. Gajski, L. Ramacahndran, Introduction to high level synthesis, IEEE Design Test Comput., October 1994.
-
-
-
-
19
-
-
0029505887
-
-
M. Genoe, et al., On the use of VHDL-based behavioral synthesis for telecom ASIC design, in: Proceedings of the International Symposium on System Synthesis ISSS'95, February 1995.
-
M. Genoe, et al., On the use of VHDL-based behavioral synthesis for telecom ASIC design, in: Proceedings of the International Symposium on System Synthesis ISSS'95, February 1995.
-
-
-
-
20
-
-
46149102214
-
-
X.-J. Zhang, K.-W. Ng, G.H. Young, High-level synthesis starting from RTL and using genetic algorithms for dynamically reconfigurable FPGAs, in: Proceedings of the 1998 ACM Fifth International Symposium on Field-Programmable.
-
X.-J. Zhang, K.-W. Ng, G.H. Young, High-level synthesis starting from RTL and using genetic algorithms for dynamically reconfigurable FPGAs, in: Proceedings of the 1998 ACM Fifth International Symposium on Field-Programmable.
-
-
-
-
21
-
-
0033356907
-
Optimal FPGA mapping and retiming with efficient initial state computation
-
Cong J., and Wu C. Optimal FPGA mapping and retiming with efficient initial state computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 11 (1999) 1595-1607
-
(1999)
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
, vol.18
, Issue.11
, pp. 1595-1607
-
-
Cong, J.1
Wu, C.2
-
22
-
-
0031645164
-
-
T.J. Callahan, P. Chong, A. DeHon, J. Wawrzynek, Fast module mapping and placement for datapaths in FPGAs of the 1998 ACM Fifth International Symposium on Field-Programmable, pp. 123-132.
-
T.J. Callahan, P. Chong, A. DeHon, J. Wawrzynek, Fast module mapping and placement for datapaths in FPGAs of the 1998 ACM Fifth International Symposium on Field-Programmable, pp. 123-132.
-
-
-
-
23
-
-
46149118187
-
-
N. Gracias, et al., Gaia: an artificial life environment for ecological systems simulation ALIFE V, pp. 124-131.
-
N. Gracias, et al., Gaia: an artificial life environment for ecological systems simulation ALIFE V, pp. 124-131.
-
-
-
-
24
-
-
46149102910
-
-
M. Nicolaidis, Une Philosophie Numérique des Univers, TIMA EDITIONS, June 2005, ISBN: 2-916187-00-6.
-
M. Nicolaidis, Une Philosophie Numérique des Univers, TIMA EDITIONS, June 2005, ISBN: 2-916187-00-6.
-
-
-
-
25
-
-
46149116783
-
-
E. Kolonis, M. Nicolaidis, Computational opportunities and CAD for nanotechnologies, Keynote, in: Workshop on Robust Computing with Nano-scale Devices: Progresses and Challenges, Nice, France, April 16-20, 2007.
-
E. Kolonis, M. Nicolaidis, Computational opportunities and CAD for nanotechnologies, Keynote, in: Workshop on Robust Computing with Nano-scale Devices: Progresses and Challenges, Nice, France, April 16-20, 2007.
-
-
-
|