Residual stress evaluation in resin-molded IC chips using finite element analysis and piezoresistive gauges

Microelectronics Reliability

Volumn 48, Issue 6, 2008, Pages 923-932

  Koganemaru, Masaaki ^a   Ikeda, Toru ^b   Miyazaki, Noriyuki ^b  

^a FUKUOKA INDUSTRIAL TECHNOLOGY CENTER   (Japan)

^b KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; ELECTRIC CONDUCTIVITY; ELECTRONIC EQUIPMENT MANUFACTURE; FINITE DIFFERENCE METHOD; FINITE ELEMENT METHOD; GAGES; MATHEMATICAL MORPHOLOGY; MODAL ANALYSIS; NUMBER THEORY; NUMERICAL METHODS; ONTOLOGY; PACKAGING; PARTIAL DIFFERENTIAL EQUATIONS; RESIDUAL STRESSES; RESINS; SEMICONDUCTOR MATERIALS; STRENGTH OF MATERIALS; STRESSES; TESTING; THICKNESS MEASUREMENT; THREE DIMENSIONAL;

(ABIOTIC AND BIOTIC) STRESS; (E ,3E) PROCESS; ELECTRONIC FUNCTIONS; ELECTRONIC PACKAGING; ELSEVIER (CO); EVALUATION METHODS; EXPERIMENTAL AND NUMERICAL METHODS; FINITE ELEMENT ANALYSIS (FEA); HIGH RESIDUAL STRESS; IC CHIPS; PIEZORESISTIVE; SEMICONDUCTOR CHIPS; SIMPLE METHODS; STRESS EVALUATIONS; STRESS-FREE TEMPERATURE; TEMPERATURE DEPENDENCES; TEST CHIPS; THREE DIMENSIONAL (3 D) MODELING;

ELECTRONICS PACKAGING;

FINITE ELEMENT ANALYSIS; MECHANICAL PROPERTIES; PACKAGING; SEMICONDUCTORS; STRESSES; SYNTHETIC POLYMERS; THREE DIMENSIONAL DESIGN;

EID: 45849090322     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2008.02.004     Document Type: Article

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